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A B C D E
1 1
Compal Confidential
NIWE2
2
Schematics Document 2
Arrandale
with Intel IBEX PEAK-M core logic
3 3
REV:0.3
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5752P
Date: Thursday, October 29, 2009 Sheet 1 of 51
A B C D E
A B C D E
Compal confidential POWER BD: LS-5754P CAP SENSOR BD:LS-5752P CARD READER BD:
File Name : POWER BT VOLUME UP LS-5753P
Z ZZ NOVO BT VOLUME DOWN RTS5138
POWER MANAGE BT MUTE HP JACK
15.6W_PCB_LA5752P VRAM 64*16 intel AUDIO ENHANCE MIC JACK
DDR3*4 Arrandale BUTTON & LED
1
page20 Clock Generator 1
PCI-E X16 (UMA/DIS) ICS9LRS3199AKLFT
page12
NVidia N11M-GE1 Socket-rPGA989
page19~23
37.5mm*37.5mm DDR3-SO-DIMM X2
level shift IC page5~9 BANK 0, 1, 2, 3 page 10,11
HDMI Dual Channel
CONN ASM1442 100MHz DDR3-800(1.5V) UP TO 8G
page25
2.7GT/s FDI *8 DMI *4 DDR3-1067(1.5V)
page24
2Channel Speaker
page33
CRT Connector
page26
Intel Ibex Peak M
2 2
LVDS Audio Codec Analog MIC_Int
AZALIA page33
Connector page27 Conexant
FCBGA 951 CX20671 page33
PCI Express
6*PCI-E BUS 25mm*25mm
Mini card Slot 1 14*USB2.0 CMOS Camera
page28
page27
PCI Express 6*SATA serial BlueTooth CONN
page 13~18
Mini card Slot 2 page37
page28
SPI ROM USB CONN X1(Right)
page37
BIOS page13 LPC BUS
3
SIM Card USB PORT X1(Left) 3
page37
page28 USB(WWAN)
RTL8111DL-VB-GR
EC New Card X1
ENE KB926D Card Reader/Audio Jack SB
page28
10/100/1G LAN page34
page29 CONN
WWAN Realtek 5138 HP X 1+
page28 MS/MS MIC_Ext X1
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD
page30 page35 page38
Touch Pad SPI ROM
page35 ESATA HDD AND USB CONN
page36 page37
SATA HDD CONN
page32
4
SATA ODD CONN 4
page32
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5752P
Date: Thursday, October 29, 2009 Sheet 2 of 51
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A B C D E
DDR3 Voltage Rails
SMBUS Control Table
N10x NEW
WLAN Thermal Cap sensor CARD PCH
SOURCE RAM BATT KE926 SODIMM CLK CHIP WWAN N10x board
+5VS Sensor
M2
+3VS SMB_EC_CK1
power
+1.5VS SMB_EC_DA1
KB926 X V
+3VALW
X X X X X X X X X
plane +3VALW
+VCCP SMB_EC_CK2
1
+5VALW +1.5V +CPU_CORE SMB_EC_DA2
KB926 X X X X X X X X X X V 1
+3VALW +3VALW
+B +VGA_CORE SMBCLK
+3VALW +1.8VS SMBDATA
PCH V X X V V X X X X V X
+3VALW +3VALW +3VS +3VS +3VS
+0.75VS SML0CLK
State +1.05VS SML0DATA
PCH
+3VALW
X X X X X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
X X V X X X +3VS
V X V
+3VS
X X
+3VALW
S0
O O O O
I2C / SMBUS ADDRESSING
S3
O O O X
2
S5 S4/AC DEVICE HEX ADDRESS 2
O O X X
DDR SO-DIMM 0 A0 10100000
S5 S4/ Battery only DDR SO-DIMM 1 A4 10100100
O X X X CLOCK GENERATOR (EXT.) D2 11010010
S5 S4/AC & Battery
don't exist X X X X
@ FUNCTION
EVT NON-USE
45@ (45 BOM)
100@ 10/100 LAN
GIGA@ GIGA LAN
UMA_HDMI@ FOR UMA HDMI components
HDMI@ FOR HDMI components PCIE PORT LIST USB PORT LIST
3
3G@ 3G(WWAN) function PORT DEVICE PORT DEVICE 3
X76@ (X76 BOM)
ESATA@ ESATA function 1 0 RIGHT SIDE
CMOS@ Camera function 2 WLAN 1 LEFT SIDE
BT@ Blue Tooth 3 LAN 2 CMOS
10M@ FOR 10M CHIP 4 3G 3 LEFT SIDE
11M@ FOR 11M CHIP 5 NEW CARD 4 RIGHT SIDE
UMA@ UMA only (Arranddale) 6 5 CARD READER
DIS@ DIS only (Arranddale) 7 6
VGA@ FOR NVIDIA PART 8 7
HYBRID@ FOR SWITCHABLE 8 WIRELESS
HU@ SWITCHABLE or UMA only 9
HD@ SWITCHABLE or DIS only 10 NEW CARD
11 BT
SKU 12
13 3G
Arrandale(dGPU) DIS@ / 100@ for EVT
4 4
DIS only
Arrandale(iGPU) UMA@ / 100@ for EVT
UMA only
Arrandale(iGPU+dGPU) VGA@+HD@+HU@+HYBRID@
SWITCHABLE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5752P
Date: Thursday, October 29, 2009 Sheet 3 of 51
A B C D E
A B C D E
VGA and DDR3 Voltage Rails (N10x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO1 IN - Hot plug detect for IFP link C N10P-GS
128bit 21.07 6.67 TBD TBD 18.25 17.34 2.06 3.09 4.09 6.14 850 0.89 75 0.14 63 0.07 55 0.18
1024MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1
GPIO3 OUT H Panel Power Enable N10P-GE
128bit 20.97 6.73 TBD TBD 19.17 17.25 2.03 3.05 4.09 6.14 840 0.88 75 0.14 63 0.07 55 0.18
1024MB
GPIO4 OUT H Panel Back-Light On/Off (PWM) DDR3
GPIO5 OUT - GPU VID0 N10P-LP
128bit 15.48 6.44 TBD TBD 13.95 11.86 1.90 2.85 3.99 5.99 810 0.85 75 0.14 63 0.07 55 0.18
1024MB
GPIO6 OUT - GPU VID1 DDR3
GPIO7 OUT - GPU VID2
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO8 I/O L Thermal Catastrophic Overtemp
FBVDDQ PCI Express I/O and I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
GPIO9 OUT L Thermal Alert (4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO10 OUT Memory VREF switch
N10M-GE
GPIO11 I/O L SLI raster sync 64bit 13.36 2.93 TBD TBD 11.89 10.70 0.66 0.99 2.16 3.24 792 0.83 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO12 IN - AC power detect pin
N10M-GS
2
GPIO13 OUT - MEM_VID orPower supply control 64bit 14.29 3.10 TBD TBD 11.53 11.53 0.70 1.05 2.28 3.42 817 0.86 75 0.14 63 0.07 100 0.33 2
512MB
DDR3
GPIO14 OUT - Power supply control
N10M-LP
GPIO15 IN - Hot plug detect for IFP Link E 64bit 8.28 2.91 TBD TBD 6.60 5.61 0.62 0.93 2.20 3.3 782 0.82 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO16 OUT - Programmable Fan Control
GPIO17 IN - The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN -
GPIO19 IN - Hot plug detect for IFP Link D
GPIO20 IN - (+3VS) VDD33
GPIO21 IN - Hot plug detect for IFP link F
PEX_VDD can ramp up any time
GPIO22 IN - SLI swap ready signal
(1.05VS)PEX_VDD
GPIO23 I/O
tNVVDD
3 3
(+VGA_CORE) NVVDD
GPIO6 GPIO5 N10M-GS N10P-GS
tNV-IFPAB_IOVDD
GPU_VID1 GPU_VID0 VGA_CORE P-State
0 0 0.8V (1.8VS)IFPAB_IOVDD
12
tNV-FBVDDQ
0 1 0.85V 12
(1.5VS) FBVDDQ
1 0 0.9V 0,10
1 1 1.0V (N10M-GS)
0.925V (N10P-GS)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5752P
Date: Thursday, October 29, 2009 Sheet 4 of 51
A B C D E
5 4 3 2 1
DDR3 Compensation Signals
SM_RCOMP0 1 2
R5 67 100_0402_1%
SM_RCOMP1 1 2
R5 66 24.9_0402_1%
SM_RCOMP2 1 2
R5 65 130_0402_1%
Layout Note:Please these
D
Layout rule 10mil width trace
length < 0.5", spacing 20mil
resistors near Processor D
J C PU1B
20_0402_1% 1 R5 60 2COMP3 AT23 COMP3 C LK_CPU_BCLK
BCLK A16 C LK_CPU_BCLK <16> + VCCP
MISC
20_0402_1% 1 R5 58 2COMP2 AT24 COMP2 BCLK# B16 CLK_CPU_BCLK#
CLK_CPU_BCLK# <16>
CLOCKS
49.9_0402_1% 1 R5 48 2COMP1 G16 AR30 CLK_CPU_ITP T17 P AD PM_EXTTS#0 1 2
COMP1 BCLK_ITP CLK_CPU_ITP# R5 61 10K_0402_5%
BCLK_ITP# AT30 T18 P AD
49.9_0402_1% 1 R5 57 2COMP0 AT26 PM_EXTTS#1 1 2
COMP0 CLK_EXP R5 62 10K_0402_5%
PEG_CLK E16 CLK_EXP <14>
D16 CLK_EXP#
PEG_CLK# CLK_EXP# <14>
TP_SKTOCC# AH24 SKTOCC#
DPLL_REF_SSCLK A18 pins unused by
A17
+ VCCP 2 1 H _CATERR# AK14
DPLL_REF_SSCLK# Clarksfield on the XDP _PREQ# R 136 1 @ 2 51_0402_1%
CATERR#
THERMAL
49.9_0402_1% R 163 rPGA989 Package
XDP_TMS R 138 1 @ 2 51_0402_1%
<16> H_ PECI
R 564 0_0402_5%
1 2 H_PECI_ISO AT15 PECI
SM_DRAMRST# F6 SM_DRAMRST# 3 XDP_TDI R 556 1 @ 2 51_0402_1%
AL1 SM_RCOMP0
SM_RCOMP[0]
+ VCCP 2 R5 69 1 68_0402_5% SM_RCOMP[1] AM1 SM_RCOMP1 X DP_TDO R 134 1 2 51_0402_5%
AN1 SM_RCOMP2
H _PROCHOT# SM_RCOMP[2]
<34,48> H _PROCHOT# AN26 PROCHOT#
AN15 PM_EXTTS#0 X DP_TCK R57 1 @ 2 51_0402_1%
PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R <10,11>
R5 63 0_0402_5% XDP_TRST# R 133 1 2 51_0402_5%
H_THERMTRIP# AK15
<16> H_THERMTRIP# THERMTRIP#
AT28 XDP_PRDY# T19 P AD R1 37
C PRDY# XDP _PREQ# XDP _DBRESET# @ C
PREQ# AP27 1 2 1K_0402_5% +3VS
AN28 X DP_TCK
TCK
1 H_ CPURST#_R XDP_TMS
+ VCCP 2 AP26 RESET_OBS# TMS AP28
CHECK INTEL DOCUMENT #385422
PWR MANAGEMENT
68_0402_5% R1 35 AT27 XDP_TRST#
TRST#
JTAG & BPM
<15> H_ PM_SYNC 1 R1 87 2 H_P M_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI Debug Port Design Guide Rev1.3
0_0402_5% AR27 X DP_TDO
TDO