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JE40 HR
DIS/UMA/Muxless Schematics Document
D


Sandy Bridge D




Intel PCH


C C



DY :None Installed ANNIE: ONLY FOR ANNIE solution.
PSL: KBC795 PSL circuit for 10mW solution installed.
DIS:DIS installed 10mW: External circuit for 10mW solution installed.
DIS_Muxless :BOTH DIS or Muxless installed 65W: for 65W adaptor installed.
DIS_PX:BOTH DIS or PX installed 90W: for 90W adaptor installed.
DIS_PX_Muxless:DIS or PX or Muxless installed.
Muxless: Muxless installed.(PX4.0)
PX:MUX installed.(PX3.0)
B
PX_Muxless:BOTH PX or Muxless installed. B



UMA:UMA installed
UMA_Muxless:BOTH UMA or Muxless installed
UMA_PX_Muxless:UMA or PX or Muxless installed




HR UMA

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3
JE40-HR -1
Date: Thursday, December 02, 2010 Sheet 1 of 102


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JE40 HR Block Diagram SYSTEM DC/DC
INPUTS
APL5916KAI
OUTPUTS
48
CPU DC/DC
NCP6131S52MNR
INPUTS OUTPUTS
42~43


##OnMainBoard
(Discrete/UMA/co-lay) 1D05V_PWR 0D85V_S0 DCBATOUT

SYSTEM DC/DC
VCC_CORE



VRAM UP6128PQDD 45
2GB/1GB/512MB
Project code : 91.4IQ01.001 INPUTS OUTPUTS
D D
88,89,90,91
PCB P/N : 48.4IQ01.0SA DCBATOUT 1D05V_VTT


DDR3 Revision : 10267-1 SYSTEM DC/DC
UP6183PQAG 41
800MHz Intel CPU INPUTS OUTPUTS
DDRIII 1066/1333 Channel A DDRIII Slot 0 5V_AUX_S5
3D3V_AUX_S5
14
Sandy Bridge 1066/1333 DCBATOUT 5V_S5
Nvidia N12P PCIe x 16 FSB: 1066 MHz
3D3V_S5

DDRIII 1066/1333 Channel B DDRIII Slot 1 SYSTEM DC/DC
(Discrete only)
15
1066/1333 UP6165BQKF 46
INPUTS OUTPUTS
PCIE x 1 USB3.0 1D5V_S3
4,5,6,7,8,9,10,11,12,13 uPD720200 DCBATOUT 0D75V_S0
83.84,85,86,87 USB x 2 DDR_VREF_S3
75
Discreet/UMA/PX Co-lay SYSTEM DC/DC
FDIx4x2 NCP5911MNTBG 44
PCIE x 1 Mini-Card
C
(UMA only) DMIx4 USB x 1 INPUTS OUTPUTS C
802.11a/b/g 65
DCBATOUT VCC_GFXCORE_PWR

HDMI Level 57 VGA
HDMI shifter PCIE x 1 RJ45 92
51 Intel RT8208BGQW
CONN 59
1000 NIC INPUTS OUTPUTS
LVDS(Dual Channel)
LCD PCH BCM57780A1 DCBATOUT VGA_CORE
49 RGB CRT 31
SD/MMC+/MS/ TI CHARGER
Cougar Point MS Pro/xD BQ24745RHDR 40
14 USB 2.0/1.1 ports INPUTS OUTPUTS
CRT ETHERNET (10/100/1000Mb)
50 DCBATOUT BT+
High Definition Audio 26
SATA ports (6) SYSTEM DC/DC
RT9025 47
PCIE ports (8)
Left Side: Mini-Card INPUTS OUTPUTS
USB x 1 LPC I/F PCIE x 1,USB x 1
66
SIM 66
B ACPI 1.1 WWAN 3D3V_S0 1D8V_S0 B



Bluetooth USB2.0 x 4 SYSTEM DC/DC
63 RT9025-25PSP 93
USB 2.0 x 1 Right Side:
17,18,19,20,21,22,23,24,25,26 USB x 1 INPUTS
26 OUTPUTS
CAMERA 1D5V_S3 1V_VGA_S0
49
3D3V_S5 1D8V_VGA_S0

AZALIA
Switches
SPI




64 SATA x 2 HDD INPUTS OUTPUTS
LPC Bus




56 1D5V_S3 1D5V_VGA_S0
3D3V_S0 3D3V_VGA_S0
Internal Analog MIC Azalia Flash ROM LPC debug port ODD
CODEC 4MB 60 71 56
PCB LAYER
HP1
ALC271X L1:Top L4:Signal
KBC
SMBus L2:VCC L5:GND
MIC IN 29 L3:Signal L6:Bottom
A
NUVOTON HR UMA A
NPCE795P 27

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH SPEAKER Title
Thermal
Touch Int. ENE P2800 Block Diagram
Fan Size Document Number Rev
PAD KB ENE P2793 28 A3
69 69 2528 JE40-HR -1
Date: Thursday, December 02, 2010 Sheet 2 of 102
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A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k weak pull-up resistor. Lane Reversal Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion1
Leave floating (internal pull-down) 0: PEG Wait for BIOS for training
Disable Danbury:

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
/GPIO[33]
3 the desired settings. If a jumper option is used to tie this signal to GND as
5V_S0
3D3V_S0
5V
3.3V 3
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V S0
VCC_GFXCORE 0.4 to 1.25V
1D8V_VGA_S0 1.8V CPU Core Rail
3D3V_VGA_S0 3.3V Graphics Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 2
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx




USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 Touch Panel / 3G SIM
1 USB Ext. port 1 (HS) I 2 C / SMBus Addresses
HURON RIVER ORB
2 Fingerprint Device Ref Des Address Hex Bus
LANE1 Mini Card2(WWAN)
3 BLUETOOTH EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Mini Card1(WLAN)SATA Table 4 Mini Card2 (WWAN) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA

LANE3 Card Reader 5 CARD READER
SATA EC SMBus 2 SML1_CLK/SML1_DATA
6 X PCH SML1_CLK/SML1_DATA
LANE4 Onboard LAN Pair Device eDP SML1_CLK/SML1_DATA
7 X
1 HR UMA
1
0 HDD1 8 USB Ext. port 4 / E-SATA /USB CHARGER
LANE5 USB3.0
1 HDD2 9 USB Ext. port 2 PCH SMBus Wistron Corporation
PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A 10 EDP CAMERA
SO-DIMMA (SPD)
SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
Digital Pot PCH_SMBDATA/PCH_SMBCLK
3 N/A 11 Mini Card1 (WLAN) G-Sensor PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock MINI PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA PCH_SMBDATA/PCH_SMBCLK Table of Content
Size Document Number Rev
LANE8 New Card 5 ESATA 13 New Card A3
-1
JE40-HR
Date: Thursday, December 02, 2010 Sheet 3 of 102
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SSID = CPU
CPU1A Signal Routing Guideline:
SANDY PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
62.10055.421 PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
Change:62.10053.611
2nd = 62.10055.321
3rd = 62.10040.821
1D05V_VTT
1 OF 9
J22 PEG_IRCOMP_R R401 1 2
PEG_ICOMPI 24D9R2F-L-GP
Note:
19 DMI_TXN[3:0]
DMI_TXN0 B27
SANDY PEG_ICOMPO J21
H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 D
Reversal and polarity inversion DMI_RX#2 PEG_RXN[0..15] 83
DMI_TXN3 B24 K33 PEG_RXN15
but only at PCH side. This is DMI_RX#3 PEG_RX#0 PEG_RXN14
19 DMI_TXP[3:0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35




DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 DMI_TX#0 PEG_RX#7 G33
DMI_RXN1 E22 G30 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 DMI_TX#2 PEG_RX#9 F35
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
DMI_RXP2 PEG_RXN1




PCI EXPRESS* - GRAPHICS
F20 DMI_TX2 PEG_RX#14 B33
DMI_RXP3 C21 C32 PEG_RXN0
DMI_TX3 PEG_RX#15
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
19 FDI_TXN[7:0] FDI_TXN0 PEG_RX2 PEG_RXP12
A21 FDI0_TX#0 PEG_RX3 H35
FDI_TXN1 H19 H32 PEG_RXP11
FDI_TXN2 FDI0_TX#1 PEG_RX4 PEG_RXP10
Note: E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 PEG_RXP9




Intel(R) FDI
Intel FDI supports both Lane F18 FDI0_TX#3 PEG_RX6 G31
FDI_TXN4 B21 F33 PEG_RXP8
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
D18 FDI1_TX#2 PEG_RX9 E35
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4 NOTE.
C
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 D34 If PEG is not implemented, the RX&TX pairs can be left as No Connect
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal
FDI_TXP3 FDI0_TX2 PEG_RX15 PEG_TXN[0..15] 83
G18 FDI0_TX3
FDI_TXP4 B20 M29 PEG_C_TXN15 C401 DIS_PX_Muxless
1 2 Do Not Stuff PEG_TXN15
FDI_TXP5 FDI1_TX0 PEG_TX#0 PEG_C_TXN14 C402 Do Not Stuff PEG_TXN14
FDI_TXP6
C19 FDI1_TX1 PEG_TX#1 M32
PEG_C_TXN13 C403
DIS_PX_Muxless
1 2
Do Not Stuff PEG_TXN13
FDI_TXP7
D19 FDI1_TX2 PEG_TX#2 M31
PEG_C_TXN12 C404
DIS_PX_Muxless
1 2