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Compal Confidential
VAWGA/B Schematics Document
2 2




AMD "Kabini" Platform
AMD 25W APU With Jaguar Core and Integrated Yangtze FCH + ATI Sun


LA-9912P REV: 1.0
3 2013-04-01 3




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/22 Deciphered Date 2015/04/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAWGA/GB
Date: Monday, April 01, 2013 Sheet 1 of 37
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Compal Confidential
Model Name : VAWGA/B

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AMD Kabini Memory BUS(DDR3)
204pin DDRIII-SO-DIMM X2
Single Channel BANK 0, 1, 2 P.8~P.9

1.5V DDRIII 1600MHz
GFX



LVDS Conn. P11 DP0
CMOS P.11 WLAN P.16 Card P.20 Touch P.16 S/B P.17

HDMI Conn. P10 DP1 Camera BT Combo Reader Screen 2.0 Conn.
AMD FT3 APU Port 3 Port 5 Port 4 Port 1 Port 0
CRT Conn. P12 DAC
2
GPP Jaguar Core USB USB2.0 2
Port 8 Port 9
GPP2 GPP1
Integrated Yangtze FCH
LAN MB P.17 MB P.17
MINI Card
Atheros BGA 769-balls 3.0 Conn. LP1 3.0 Conn. LP2
(WLAN/BT)
P16 AR8162/8172
P14 Port 0 Port 1
USB
Transformer USB3.0
RJ45 HDA HD Audio
P15
BIOS (4M) SPI
P.5 SATA

LPC Gen3 Port 0 Port 1
Int.KBD P.20 ENE
Audio
KBC9012 HDD ODD
P.18 Conexant
Conn. Conn.
P.13 P.13 CX20757
PS2 P.21
3
P.4~P.7 3

Touch Pad Thermal Sensor
P.20 P.19




Int. MIC Int. Speaker Conn. Audio Combo Jacks
page 21 page 21
HP & MIC
page 21

Sub-borad
15"
14"
IO/B ODD/B
LS9633P LS9634P
page 20 page 13

4 Power/B LED/B 4

LS9631P LS9635P
page 20 page 20

USB/B Security Classification Compal Secret Data Compal Electronics, Inc.
LS9632P
Issued Date 2012/04/22 Deciphered Date 2015/04/22 Title
page 17 BLOCK DIAGRAMS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAWGA/GB
Date: Thursday, March 28, 2013 Sheet 2 of 37
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Voltage Rails BOARD ID Table
Board ID PCB Revision SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Power Plane Description S0 S3 S5 0 MP
VIN Adapter power supply (19V) ON ON ON 1 PVT Full ON HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON 2 DVT
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
+APU_CORE Core voltage for APU ON OFF OFF 3 EVT
1
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 4 S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF 1

+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF 5 S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+VDDCI 0.95-1.2V switched power rail ON OFF OFF 6
+3VALW 3.3V always on power rail ON ON OFF 7 S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VS 3.3V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Board ID / SKU ID Table for AD channel USB OC MAPPING
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
OC# USB Port
+0.95VALW 0.95V always on power rail ON OFF OFF R1562 100K +/- 5%
+0.95VS 0.95V switched power rail ON OFF OFF Board ID R1564 V AD_BID min V AD_BID typ V AD_BID max 0 USB20 port0
+1.5V 1.5V power rail for APU and DDR ON ON OFF 0 0 0 V 0 V 0 V 1 USB20 port1,2,8,9 USB30 port0,1
+1.5VS 1.5V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 2
+3VGS 3.3V switched power rail for VGA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 3
+1.8VGS 1.8V switched power rail for VGA ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+1.5VGS 1.5V switched power rail for VGA ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V BOM Structure Table
+0.95VGS 0.95V switched power rail for VGA ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
BOM Structure BTO Item
+5VALW 5V always on power rail ON ON ON 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V A6 R3 BGA APU 2
A6@
+VSB VSB always on power rail ON ON ON
A4@ A4 R3 BGA APU
+RTC_APU RTC power ON ON ON
E2@ E2 R3 BGA APU
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
E1@ E1 R3 BGA APU
E1PC@ E1 PC BGA APU
elbaT lortnoC SUBMS X4@ X4 ES2 BGA APU
lamrehT X5 ES2 BGA APU
NALW X5@
ECRUOS AGV TTAB 2109BK NAWW MMIDOS HCF rosneS UPA 2312DTR APU PCIE PORT LIST X2 ES2 BGA APU
X2@
1KC_CE_BMS Port Device EMICU@ CardReader EMI Un pop
1AD_CE_BMS
2109BK
WLAV3+
X V
WLAV3+
X X X X X X X EMICP@ CardReadear EMI pop
0 EMIUSB2RU@ Right USB2.0 port EMI un pop
1 LAN
EMIUSB2RP@ Right USB2.0 port EMI pop
0KLCS_UPA 2 WLAN
USB2R@ Right USB2.0 port component
0ATADS_UPA
UPA X X X V
SV3+
V
SV3+
X X X X 3 SUN@ SUN PRO GPU (R3 compal part)
SV3+
MARS@ MARS XT GPU (R1 compal part)
2KC_CE_BMS
2109BK V X X X X V V 14@ for 14" componect
3
2AD_CE_BMS SV3+
SV3+ SV3+
X SV3+
X 15@ for 15" componect 3


PX@ Common VGA circuit
CMOS@ CMOS Camera part
HDMI@ HDMI part
USB Port Table
EMIGASP@ Gastube
3 External 8162@ Ateros AR8162 LAN Chip
EC SM Bus1 address EC SM Bus2 address USB 2.0 USB 3.0 Port USB Port 8172@ Ateros AR8172 LAN Chip
Device Address HEX Device Address HEX 0 RIGHT USB SWR@ LAN Switching mode
Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH 1 Touch Screen LDO@ LAN LDO mode
SB-TSI (APU) 1001 100X b 98H 2 THERMAL@ Lenovo Thermal Sensor
3 Camera ME@ ME part
VGA Internal Thermal 1000 001X b 82H 4 CardReader UMA@ UMA part
5 WLAN/BT Combo @ Unpop
6 LEFT USB (for colay) ZODD@ Zero Power ODD part
7 LEFT USB (for colay) TS@ Touch Screen
APU
0 8 LEFT USB3.0 EMIP@ EMI pop component
4 SM Bus address XHCI
1 9 LEFT USB3.0 EMIU@ EMI Un pop component 4


Device Address HEX ESDP@ ESD pop component
DDR DIMM1 1010 000Xb A0H ESDU@ ESD Un pop component
DDR DIMM2 1010 001Xb A2H
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/22 Deciphered Date 2015/04/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTES LIST
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAWGA/GB
Date: Monday, April 01, 2013 Sheet 3 of 37
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UAPUA HDMI & LVDS should be reverse in KABINI:
<8,9> DDRAB_SMA[15..0] DDRAB_SDQ[63..0] <8,9>
DDRAB_SMA0 AG38
MEMORY
B30 DDRAB_SDQ0
APU TX0 to Connector TX2 ; APU TX1 to Connector TX1 UAPUC
M_ADD0 M_DATA0
DDRAB_SMA1 W35 M_ADD1 M_DATA1 A32 DDRAB_SDQ1 APU TX2 to Connector TX0 ; APU TX3 to Connector CLK DISPLAY/SVI2/JTAG/TEST
DDRAB_SMA2 W38 M_ADD2 M_DATA2 B35 DDRAB_SDQ2 <10>
A9 TDP1_TXP0 DP_150_ZVSS B16 DP_150_ZVSS
DP2_TXP0
DDRAB_SMA3 W34 M_ADD3 M_DATA3 A36 DDRAB_SDQ3 <10>
B9 TDP1_TXN0 DP_2K_ZVSS A21 DP_2K_ZVSS R400 1 2 2K_0402_1%
DDRAB_SMA4 U38 B29 DDRAB_SDQ4 DP2_TXN0 B17
M_ADD4 M_DATA4 DP_BLON
ENBKL <18>
DDRAB_SMA5 U37 M_ADD5 M_DATA5 A30 DDRAB_SDQ5 A10 TDP1_TXP1 DP_DIGON A17
<10> DP2_TXP1 APU_ENVDD <11>
DDRAB_SMA6 U34 M_ADD6 M_DATA6 A34 DDRAB_SDQ6 B10 TDP1_TXN1 DP_VARY_BL A18
<10> DP2_TXN1 APU_INVT_PWM <11>
DDRAB_SMA7 R35 M_ADD7 M_DATA7 B34 DDRAB_SDQ7 HDMI
DDRAB_SMA8 R38 M_ADD8 A11 TDP1_TXP2
<10> DP2_TXP2
DDRAB_SMA9 N38 M_ADD9 M_DATA8 B37 DDRAB_SDQ8 B11 TDP1_TXN2 TDP1_AUXP D17
<10> DP2_TXN2 HDMI_CLK <10,12>
DDRAB_SMA10 AG34 M_ADD10 M_DATA9 A38 DDRAB_SDQ9 TDP1_AUXN E17
HDMI_DATA <10,12>
DDRAB_SMA11 R34 M_ADD11 M_DATA10 D40 DDRAB_SDQ10 <10>
A12 TDP1_TXP3
DP2_TXP3
DDRAB_SMA12 N37 M_ADD12 M_DATA11 D41 DDRAB_SDQ11 B12 TDP1_TXN3 TDP1_HPD H19
1 <10> DP2_TXN3 HDMI_DET <10> 1
DDRAB_SMA13 AN34 M_ADD13 M_DATA12 B36 DDRAB_SDQ12
DDRAB_SMA14 L38 M_ADD14 M_DATA13 A37 DDRAB_SDQ13 A4 LTDP0_TXP0 LTDP0_AUXP D15
<11> LVDS_A2 EDID_CLK <11>
DDRAB_SMA15 L35 M_ADD15 M_DATA14 B41 DDRAB_SDQ14 B4 LTDP0_TXN0 LTDP0_AUXN E15
<11> LVDS_A2# EDID_DATA <11>
M_DATA15 C40 DDRAB_SDQ15
AJ38 M_BANK0 A5 LTDP0_TXP1 LTDP0_HPD H17 R897 1 2 100K_0402_5%
<8,9> DDRAB_SBS0# <11> LVDS_A1 +3VS
AG35 M_BANK1 M_DATA16 F40 DDRAB_SDQ16 B5 LTDP0_TXN1
<8,9> DDRAB_SBS1# <11> LVDS_A1#
N34 M_BANK2 M_DATA17 F41 DDRAB_SDQ17 LVDS DAC_RED B14
<8,9> DDRAB_SBS2# DAC_RED <12>
M_DATA18 K40 DDRAB_SDQ18 A6 LTDP0_TXP2
<8,9> DDRAB_SDM[7..0] <11> LVDS_A0
DDRAB_SDM0 B32 M_DM0 M_DATA19 K41 DDRAB_SDQ19 B6 LTDP0_TXN2 DAC_GREEN A14
<11> LVDS_A0# DAC_GRN <12>
DDRAB_SDM1 B38 M_DM1 M_DATA20 E40 DDRAB_SDQ20 CRT
DDRAB_SDM2 G40 M_DM2 M_DATA21 E41 DDRAB_SDQ21 A7 LTDP0_TXP3 DAC_BLUE B15
<11> LVDS_ACLK DAC_BLU <12>
DDRAB_SDM3 N41 M_DM3 M_DATA22 J40 DDRAB_SDQ22 B7 LTDP0_TXN3
<11> LVDS_ACLK#
DDRAB_SDM4 AG40 M_DM4 M_DATA23 J41 DDRAB_SDQ23
DDRAB_SDM5 AN41 M_DM5 DAC_HSYNC G19 CRT_HSYNC
CRT_HSYNC <12>
DDRAB_SDM6 AY40 M_DM6 M_DATA24 M41 DDRAB_SDQ24 K15 DISP_CLKIN_H DAC_VSYNC E19
CRT_VSYNC <12>
DDRAB_SDM7 AY34 M_DM7 M_DATA25 N40 DDRAB_SDQ25 H15 DISP_CLKIN_L
Y40 M_DM8 M_DATA26 T41 DDRAB_SDQ26 DAC_SCL D19
CRT_DDC_CLK <12>
M_DATA27 U40 DDRAB_SDQ27 APU_SVT G31 SVT DAC_SDA D21
<29> APU_SVT CRT_DDC_DATA <12>
B33 M_DQS_H0 M_DATA28 L40 DDRAB_SDQ28 APU_SVC D27 SVC
<8,9> DDRAB_SDQS0 <29> APU_SVC
A33 M_DQS_L0 M_DATA29 M40 DDRAB_SDQ29 APU_SVD E29 SVD DAC_ZVSS A16 DAC_ZVSS R416 1 2 499_0402_1%
<8,9> DDRAB_SDQS0# <29> APU_SVD
B40 M_DQS_H1 M_DATA30 R40 DDRAB_SDQ30
<8,9> DDRAB_SDQS1 +3VS
A40 M_DQS_L1 M_DATA31 T40 DDRAB_SDQ31 R124 1 @ 2 0_0402_5% APU_SIC B22 SIC H27
THERMDA
<8,9> DDRAB_SDQS1# <18,19> EC_SMB_CK2
H41 M_DQS_H2 R127 1 @ 2 0_0402_5% APU_SID B21 SID H29
THERMDC
<8,9> DDRAB_SDQS2 <18,19> EC_SMB_DA2
H40 M_DQS_L2 M_DATA32 AF40 DDRAB_SDQ32 DIECRACKMON D25
<8,9> DDRAB_SDQS2# P41 M_DQS_H3 M_DATA33 AF41 DDRAB_SDQ33 APU_RST# B20 APU_RST_L BP0 A27 APU_BP0
<8,9> DDRAB_SDQS3 P40 M_DQS_L3 M_DATA34 AK40 DDRAB_SDQ34 R117 1 @ 2 0_0402_5% LDT_RST# A20 LDT_RST_L BP1 B27 APU_BP1 EDID_CLK R255 2 1 4.7K_0402_5%
<8,9> DDRAB_SDQS3# AH41 M_DQS_H4 M_DATA35 AK41 DDRAB_SDQ35 BP2 A26 APU_BP2 EDID_DATA R256 2 1 4.7K_0402_5%
<8,9> DDRAB_SDQS4 AH40 M_DQS_L4 M_DATA36 AE40 DDRAB_SDQ36 APU_PWRGD B19 APU_PWROK BP3 B26 APU_BP3
<8,9> DDRAB_SDQS4# <29> APU_PWRGD
AP41 M_DQS_H5 M_DATA37 AE41 DDRAB_SDQ37 R118 1 @ 2 0_0402_5% LDT_PWRGD A19 LDT_PWROK PLLTEST1 B28 APU_PLLTEST1
<8,9> DDRAB_SDQS5 AP40 M_DQS_L5 M_DATA38 AJ40 DDRAB_SDQ38 PLLTEST0 A28 APU_PLLTEST0 RP23
<8,9> DDRAB_SDQS5# BA40 M_DQS_H6 M_DATA39 AJ41 DDRAB_SDQ39 R120 1 @ 2 0_0402_5% APU_PROCHOT# A22 PROCHOT_L BYPASSCLK_H B24 APU_BPCLK_H 8 1 DAC_BLU
<8,9> DDRAB_SDQS6 <18,24,29,6> H_PROCHOT#
AY41 M_DQS_L6 APU_ALERT# B18 ALERT_L BYPASSCLK_L A24 APU_BPCLK_L