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5 4 3 2 1
SJV50-TR Block Diagram
PCB Layer Stackup
L1: Signal 1
L2: VCC
Project code: 91.4FM01.001
DDR2 SODIMM L3: Inner Signal 2
DDR II 667/800
AMD Tigris CPU PCB P/N : 48.4FM01.011
D DIMM1
16,17
G792 REVISION : 09228-1
L4: Inner Signal 3 D
S1G3 (35W) 33
USB BD :08652-1M
L5: GND
DDR2 SODIMM DDR II 667/800 PWR BD :08653-1
L6: Signal 4
638-Pin uFCPGA638 4,5,
DIMM2
16,17 6,7
Video RAM CPU V_CORE
HyperTransport
OUT
16x16 64Mbx16x4 55,56
IN
CLK GEN. 14.318MHz HDMI INPUT OUTPUT
20
ICS9LPRS480BKLFT DCBATOUT VCC_CORE_S0
3 LCD
North Bridge PCIex16 18
GPU ON BOARD
AMD RS880M M92-M2 SYSTEM DC/DC
27MHz 50, 51, 52, 53, 54, 55, 56 CRT
CPU I/F LVDS, CRT I/F 19 INPUT OUTPUT
INTEGRATED GRAHPICS 1D1V_S0
C
PCI-E x 1
LAN
10/100/1000 TXFM RJ45 DCBATOUT 1D2V_S0
1D8V_S3
C
BCM5764/5784
26 26
8,9,10 25
SYSTEM DC/DC
25MHz
PCI-E x 4 Mini Card(1)Half INPUT OUTPUT
DCBATOUT 5V_S5
802.11a/b/g/n 32 3D3V_S5
PCI-E x 2
South Bridge 25MHz Mini Card(2)
29 Codec AZALIA SYSTEM LDO
802.11a/b/g/n 32
CX20561 32.768KHz
MIC In 27 AMD SB710 INPUT OUTPUT
USB 2.0/1.1 ports 1D8V_S3 0D9V_S3
ETHERNET (10/100/1000Mb)
High Definition Audio SYSTEM LDO
29 SD/ MMC/ MS INPUT OUTPUT
ATA 66/100 USB CardReader
B MS PRO/ XD B
Line Out RTS5159 31 5 in 1 31 3D3V_S5 1D2V_S5
ACPI 1.1 3D3V_S0 2D5V_S0
AZALIA
3D3V_S0 1D5V_S0
LPC I/F
AMP SYSTEM LDO
29 G1454 PCI/PCI BRIDGE LPC BUS
28 INPUT OUTPUT
INT.SPKR 5V_AUX_S5
DCBATOUT
MODEM USB SPI I/F BIOS LPC 3D3V_AUX_S5
11,12,13,14,15 KBC
Winbond W25X16-VSS
RJ11 MDC Card 32.768KHz 35 DEBUG
30 30 WPC773L CONN. 35 Battery Charger
34
USB x 4
SATA INPUTS OUTPUTS
CCD .3M
USB
HDD 21 18 Touch INT. AD+ DCBATOUT
Pad 36 KB 34 BAT+
A A
USB MINI USB
4 Port BlueTooth Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
24 23
Hsichih, Taipei
Title
CDROM SATA BLOCK DIAGRAM
Size Document Number Rev
22 A3
SJV50-TR -1
Date: Monday, June 29, 2009 Sheet 1 of 59
5 4 3 2 1
5 4 3 2 1
USB
PCIE Pair Device
D PCIE0 LAN 11 CardReader D
10 CCD
PCIE1 MINICARD1 9 Mini Card2
8 USB4
PCIE2 MINICARD2 7 USB1 OCP2#
6 USB2 OCP1#
PCIE3
5 BlueTooth
4 NC
3 NC
2 NC
1 Mini Card1
0 USB3 OCP0#
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB&PCIE ROUTING
Size Document Number Rev
A3 SJV50-TR -1
Date: Monday, June 29, 2009 Sheet 2 of 59
5 4 3 2 1
A B C D E
3D3V_S0 3D3V_CLK_VDD
3D3V_S0
1 R175 2 R164
0R0603-PAD 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
C432 C428 C396 C433 C438 C422 C394 C436
SC4D7U6D3V3KX-GP
Due to PLL issue on current clock chip, the SBlink clock
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C400 C398
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
3000mA.80ohm DY
2
2
2
2
2
2
2
2
Future clock chip revision will fix this.
DY-C.D.
2
2
4 4
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
reserved for debug purpose.
1 R176 2
0R0603-PAD
1D2V_S0 1D1V_CLK_VDDIO 82.30005.A11 SB 980601
1 R163 2 2ND = 82.30005.881 C414
0R3J-0-U-GP GEN_XTAL_IN 2 1
1
1
1
1
1
1
1
C415 C406 C399 C397 C395 C437 C434 3D3V_CLK_VDD SC33P50V2JN-3GP
DY
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
U24 X5
2
2
2
2
2
2
2
DY-C.D.
DY-C.D.
1D1V_CLK_VDDIO X-14D3181MHZ-GP
26 61 CL=20pF 30ppm C405 SC33P50V2JN-3GP
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 2 1
48 G29
VDDCPU SB_MEM_480_CLK 2 G28 1
47 VDDCPU_IO SMBCLK 2 SB_MEM_CLK 12,16,17
3 SB_MEM_480_DAT2 1
SMBDAT SB_MEM_DAT 12,16,17
16 GAP-CLOSE
VDDSRC GAP-CLOSE
17 VDDSRC_IO
11 VDDSRC_IO ATIG0T_LPRS 30 CLK_PCIE_PEG 50
3D3V_CLK_VDD 29
ATIG0C_LPRS CLK_PCIE_PEG# 50
35 VDDSB_SRC ATIG1T_LPRS 28
34 VDDSB_SRC_IO ATIG1C_LPRS 27 CLK_NB_GFX 9
CLK_NB_GFX# 9
1 R172 2 40 VDDSATA
3 0R0603-PAD 4 23 CLKREQ0#1 TP200 TPAD14-GP 3
VDD CLKREQ0#
1
C427 CLKREQ1#1 TP206 TPAD14-GP
SC1U10V2KX-1GP VDD_REF
55
56
VDDHTT CLKREQ1# 45
44 CLKREQ2#1 TP207 TPAD14-GP
CLKREQ# Internal
VDDREF CLKREQ2#
3D3V_48MPWR_S0 63 39 CLKREQ3#1 TP204 TPAD14-GP pull high
2
VDD48 CLKREQ3# CLKREQ4#1 TP203 TPAD14-GP
CLKREQ4# 38
PD# 51 PD#
11 CLK_PCIE_SB CPUKG0T_LPRS 50 CPU_CLK 6
11 CLK_PCIE_SB# CPUKG0C_LPRS 49 CPU_CLK# 6
22
21
SRC0T_LPRS
64 CLK_48 2 1R161
-1 98625
25 CLK_PCIE_LAN SRC0C_LPRS 48MHZ_0 CLK48_USB 12
25 CLK_PCIE_LAN# 20 22R2J-2-GP
SRC1T_LPRS R162
19 SRC1C_LPRS 2 1 CLK48_5159E 31
15 59 REF0 22R2J-2-GP
9 CLK_NB_GPPSB SRC2T_LPRS REF0/SEL_HTT66 REF1
9 CLK_NB_GPPSB# 14 SRC2C_LPRS REF1/SEL_SATA 58
32 CLK_PCIE_MINI1 13 57 REF2
SRC3T_LPRS REF2/SEL_27
1
1
12 C855 C856
32 CLK_PCIE_MINI1# SRC3C_LPRS 20090107_SB mofify
RF_DY
SC22P50V2JN-4GP
RF_DY