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A B C D E
Kirin (FX2 with NS) VER : 1A
1 1
DDRII-SODIMM1 AMD S1
PG 7,8 Turion 64 Rev.F Dual-Core/ CPU VR CLOCKS Thermal SYSTEM VCCP BATT AC/BATT RUN
533 MHz DDR II Sempron Rev.F Single-Core Monitor DDR II CHARGER Conn. POWER SW
Dual-Core 35W / Single-Core 25W
PG 37 PG 13 PG 35 PG 38 PG 39 PG 36 PG 41 PG 40
DDRII-SODIMM2 (638 S1g1 socket)
PG 7,8
PG 3,4,5,6
HT_LINK
PCI-E(1)
Express Card
USB2.0(P1)
Panel Connector LVDS RS485 A12 PG 25
PG 18 PCI-E(2)
2 Mini Card (WLAN) 2
USB2.0(P5)
465 FCBGA PG 24
VGA Conn. VGA
PG 19
USB2.0(P0,P2)
PG 9,10,11,12 USB Conn. Right Side x2
PG 28 VGA Conn. LAN with Power
USB-3 USB-2 Modem trancformet Jack
USB2.0(P4,P6)
SATA - HDD SATA II USB Conn. Back side x2 BCM4401
A_LINK
PG 23 PG 28
Dash Conn.
LCD Conn.
USB-0,1
LID SW
Fixed PATA ODD IDE Conn
Mini Card Latch R5C832
BCM4401
PG 23 SB600 A13 RJ45/Magnetics
(B0)
Phone Jack/MIC
PG 33 PG 34
549 BGA ATI RS485M
3 AC97/Azalia
33MHz PCI 3 in 1 Card
3
PG 14,15,16,17 3 in 1 Conn. ATI SB600 3 in 1 Conn.
R5C832 AMD S1 Socket
PG 20,21 PG 22 Mini Card Conn.
AUDIO MDC
Fan K/B Conn.
PG 31 PG 26 LPC Conn
DDR II PCB1
Mini PCI(for debug) FX2 MB
TP Conn.
SATA Conn.
ODD Conn.
Tip PG 42
Audio Jacks KBC
Ring
Express Conn.
PG 32
PG 26 NS97551/87541
PG 27 R-BATT Conn.
X-Bus
KB Touch Flash SPK Conn.
Conn. Pad ROM Battery Conn.
4 4
PG 35 PG 30 PG 27
QUANTA
Title
COMPUTER
BLOCK DIAGRAM
Size Document Number Rev
FX2 1A
Date: Friday, May 05, 2006 Sheet 1 of 47
A B C D E
A B C D E
INDEX
1 Page Description 1
1 BLOCK DIAGRAM
2 FRONT PAGE
3 ATHLON64 HT I/F
4 ATHLON64 DDRII MEMORY
5 ATHLON64 CTRL & DEBUG
6 ATHLON64 PWR & GND
7 DDRII SODIMMX2
8 DDRII TERMINATION
9 RS485-HT LINK0 I/F
10 RS485-PCIE LINK I/F
11 RS485-LVDS
12 RS485-POWER
13 CLOCK GENERATOR
14 SB600M-PCIE/PCI/LPC
15 SB600M ACPI/USB/AC97
2 16 SB600M HDD/POWER 2
17 SB600M STRAPS
18 LCD CONN
19 CRT
20 5C832/PCI
21 CARD READER
22 CARD READER CONN
23 SATA HDD & PATA ODD
24 MINI Card
25 MINI Card
26 MDC CONN
27 PC97551 & FLASH
28 USB
29 EMI & Screw hole
30 SWITCH & TP & LED
31 Azelia CODEC
3 32 AUDIO CONN 3
33 LAN(BCM4401)
34 LAN JACK
35 KB & THERMAL & FAN
36 CHARGER (MAX8731)
37 VHCORE (MAX8774)
38 SYSTEM (MAX8734)
39 VCCP & DDR2 (MAX8743)
40 RUN POWER SW
41 DCIN,Batt
42 MINI PCI(for debug)
43 Power On Sequence
44 Power On Diagram
45 SMBUS BLOCK
4 4
QUANTA
Title
COMPUTER
FRONT PAGE
Size Document Number Rev
FX2 1A
Date: Thursday, May 04, 2006 Sheet 2 of 47
A B C D E
5 4 3 2 1
D D
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN U1A
C1
D4 VLDT_A3 VLDT_B3 AE5
D3 VLDT_A2 VLDT_B2 AE4
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
4.7U_6.3V_0603
(9) HT_CADIN15_P N5 L0_CADIN_H15 L0_CADOUT_H15 T4 HT_CADOUT15_P (9)
(9) HT_CADIN15_N P5 L0_CADIN_L15 L0_CADOUT_L15 T3 HT_CADOUT15_N (9)
(9) HT_CADIN14_P M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CADOUT14_P (9)
(9) HT_CADIN14_N M4 L0_CADIN_L14 L0_CADOUT_L14 U5 HT_CADOUT14_N (9)
(9) HT_CADIN13_P L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CADOUT13_P (9)
M5 V3 +1.2V_VCCP VLDT_RUN
(9) HT_CADIN13_N L0_CADIN_L13 L0_CADOUT_L13 HT_CADOUT13_N (9)
C (9) HT_CADIN12_P K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CADOUT12_P (9) C
K4 W5 L1
(9) HT_CADIN12_N L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUT12_N (9)
H3 AB5 FBJ3216HS800_1206
(9) HT_CADIN11_P L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUT11_P (9)
(9) HT_CADIN11_N H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CADOUT11_N (9)
(9) HT_CADIN10_P G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 HT_CADOUT10_P (9)
(9) HT_CADIN10_N H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 HT_CADOUT10_N (9)
(9) HT_CADIN9_P F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 HT_CADOUT9_P (9) changed from 10p to
(9) HT_CADIN9_N F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CADOUT9_N (9) 180p as AMD suggestion
E5 AD4 L2
(9) HT_CADIN8_P L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUT8_P (9)
F5 AD3 FBJ3216HS800_1206
(9) HT_CADIN8_N L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUT8_N (9)
(9) HT_CADIN7_P N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CADOUT7_P (9) 80 ohm(4A)
1
1
N2 R1 C2 C3 C4 C5 C6 C7
(9) HT_CADIN7_N L0_CADIN_L7 L0_CADOUT_L7 HT_CADOUT7_N (9)
(9) HT_CADIN6_P L1 L0_CADIN_H6 L0_CADOUT_H6 U2 HT_CADOUT6_P (9)
M1 U3 4.7U_6.3V_0603 4.7U_6.3V_0603 .22U_6.3V .22U_6.3V 180P_50V 180P_50V
(9) HT_CADIN6_N L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUT6_N (9)
2
2
(9) HT_CADIN5_P L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CADOUT5_P (9)
(9) HT_CADIN5_N L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CADOUT5_N (9)
(9) HT_CADIN4_P J1 L0_CADIN_H4 L0_CADOUT_H4 W2 HT_CADOUT4_P (9)
(9) HT_CADIN4_N K1 L0_CADIN_L4 L0_CADOUT_L4 W3 HT_CADOUT4_N (9)
(9) HT_CADIN3_P G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CADOUT3_P (9)
H1 AA3
(9) HT_CADIN3_N
G3
L0_CADIN_L3 L0_CADOUT_L3
AB1
HT_CADOUT3_N (9) LAYOUT: Place bypass cap on topside of board
(9) HT_CADIN2_P L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUT2_P (9)
(9) HT_CADIN2_N G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CADOUT2_N (9) NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
(9) HT_CADIN1_P E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CADOUT1_P (9) TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
(9) HT_CADIN1_N F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CADOUT1_N (9) TO OTHER HT POWER PINS
B
(9) HT_CADIN0_P E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUT0_P (9) PLACE CLOSE TO VLDT0 POWER PINS B
(9) HT_CADIN0_N E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CADOUT0_N (9)
(9) HT_CLKIN1_P J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CLKOUT1_P (9)
(9) HT_CLKIN1_N K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CLKOUT1_N (9)
(9) HT_CLKIN0_P J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CLKOUT0_P (9)
VLDT_RUN J2 W1
(9) HT_CLKIN0_N L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUT0_N (9)
R2 49.9/F HT_CTLIN1_P P3 T5 HT_CPU_CTLOUT1_P
L0_CTLIN_H1 L0_CTLOUT_H1 T1
HT_CTLIN1_N P4 R5 HT_CPU_CTLOUT1_N
49.9/F L0_CTLIN_L1 L0_CTLOUT_L1 T2
R1
(9) HT_CTLIN0_P N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CTLOUT0_P (9)
(9) HT_CTLIN0_N P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CTLOUT0_N (9)
Athlon 64 S1
Processor Socket
QUANTA
A A
Title
COMPUTER
ATHLON64 HT I/F
Size Document Number Rev
FX2 1A
Date: Friday, May 05, 2006 Sheet 3 of 47
5 4 3 2 1
A B C D E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER +1.8V_SUS
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE Processor DDR2 Memory Interface
R3
2K/F U1C
M_B_DQ63 AD11 AA12 M_A_DQ63
(7) M_B_DQ[0..63] MB_DATA63 MA_DATA63 M_A_DQ[0..63] (7)
CPU_M_VREF M_B_DQ62 AF11 AB12 M_A_DQ62
M_B_DQ61 MB_DATA62 MA_DATA62 M_A_DQ61
AF14 MB_DATA61 MA_DATA61 AA14
4 M_B_DQ60 AE14 AB14 M_A_DQ60 4
M_B_DQ59 MB_DATA60 MA_DATA60 M_A_DQ59
for +0.9V_DDR_VTT Y11 MB_DATA59 MA_DATA59 W11
C8 C9 R4 M_B_DQ58 AB11 Y12 M_A_DQ58
feedback MB_DATA58 MA_DATA58
.1U_10V 1000p_50V 2K/F M_B_DQ57 AC12 AD13 M_A_DQ57
M_B_DQ56 MB_DATA57 MA_DATA57 M_A_DQ56
AF13 MB_DATA56 MA_DATA56 AB13
VTT_SENSE M_B_DQ55 AF15 AD15 M_A_DQ55
(39) VTT_SENSE MB_DATA55 MA_DATA55
M_B_DQ54 AF16 AB15 M_A_DQ54
M_B_DQ53 MB_DATA54 MA_DATA54 M_A_DQ53
AC18 MB_DATA53 MA_DATA53 AB17
C677 1 M_B_DQ52 AF19 MB_DATA52 MA_DATA52 Y17 M_A_DQ52
+1.8V_SUS 470P_50V M_B_DQ51 AD14 Y14 M_A_DQ51
U1B +0.9V_DDR_VTT M_B_DQ50 MB_DATA51 MA_DATA51 M_A_DQ50
AC14 MB_DATA50 MA_DATA50 W14
2
M_B_DQ49 AE18 W16 M_A_DQ49
MB_DATA49 MA_DATA49
2
W17 D10 M_B_DQ48 AD18 AD17 M_A_DQ48
R6 MEMVREF VTT1 M_B_DQ47 MB_DATA48 MA_DATA48 M_A_DQ47
VTT2 C10 AD20 MB_DATA47 MA_DATA47 Y18
39.2/F Y10 B10 M_B_DQ46 AC20 AD19 M_A_DQ46
R566 0 VTT_SENSE VTT3 M_B_DQ45 MB_DATA46 MA_DATA46 M_A_DQ45
VTT4 AD10 AF23 MB_DATA45 MA_DATA45 AD21
W10 M_B_DQ44 AF24 AB21 M_A_DQ44
VTT5 MB_DATA44 MA_DATA44
1
M_ZN AE10 AC10 M_B_DQ43 AF20 AB18 M_A_DQ43
M_ZP MEMZN VTT6 M_B_DQ42 MB_DATA43 MA_DATA43 M_A_DQ42
AF10 MEMZP VTT7 AB10 AE20 MB_DATA42 MA_DATA42 AA18
AA10 M_B_DQ41 AD22 AA20 M_A_DQ41
VTT8 MB_DATA41 MA_DATA41
2
A10 M_B_DQ40 AC22 Y20 M_A_DQ40
R5 VTT9 M_B_DQ39 MB_DATA40 MA_DATA40 M_A_DQ39
AE25 MB_DATA39 MA_DATA39 AA22
39.2/F V19 Y16 M_B_DQ38 AD26 Y22 M_A_DQ38
(7,8) M_A_CS#3 MA0_CS_L3 MA0_CLK_H2 M_CLKOUT1 (7) MB_DATA38 MA_DATA38
J22 AA16 M_B_DQ37 AA25 W21 M_A_DQ37
(7,8) M_A_CS#2 MA0_CS_L2 MA0_CLK_L2 M_CLKOUT1# (7) MB_DATA37 MA_DATA37
V22 E16 M_B_DQ36 AA26 W22 M_A_DQ36
(7,8) M_A_CS#1 MA0_CS_L1 MA0_CLK_H1 M_CLKOUT0 (7) MB_DATA36 MA_DATA36
1
T19 F16 M_B_DQ35 AE24 AA21 M_A_DQ35
(7,8) M_A_CS#0 MA0_CS_L0 MA0_CLK_L1 M_CLKOUT0# (7) MB_DATA35 MA_DATA35
M_B_DQ34 AD24 AB22 M_A_DQ34
M_B_DQ33 MB_DATA34 MA_DATA34 M_A_DQ33
(7,8) M_B_CS#3 Y26 MB0_CS_L3 MB0_CLK_H2 AF18 M_CLKOUT4 (7) AA23 MB_DATA33 MA_DATA33 AB24
J24 AF17 M_B_DQ32 AA24 Y24 M_A_DQ32
(7,8) M_B_CS#2 MB0_CS_L2 MB0_CLK_L2 M_CLKOUT4# (7) MB_DATA32 MA_DATA32
W24 A17 M_B_DQ31 G24 H22 M_A_DQ31
(7,8) M_B_CS#1 MB0_CS_L1 MB0_CLK_H1 M_CLKOUT3 (7) MB_DATA31 MA_DATA31
U23 A18 M_B_DQ30 G23 H20 M_A_DQ30
(7,8) M_B_CS#0 MB0_CS_L0 MB0_CLK_L1 M_CLKOUT3# (7) MB_DATA30 MA_DATA30
M_B_DQ29 D26 E22 M_A_DQ29
M_B_DQ28 MB_DATA29 MA_DATA29 M_A_DQ28
PLACE THEM CLOSE TO (7,8) M_CKE3 H26 MB_CKE1 MB0_ODT1 W23 M_ODT3 (7,8) C26 MB_DATA28 MA_DATA28 E21
J23 W26 M_B_DQ27 G26 J19 M_A_DQ27
CPU WITHIN 1" (7,8) M_CKE2 MB_CKE0 MB0_ODT0 M_ODT2 (7,8) MB_DATA27 MA_DATA27
J20 V20 M_B_DQ26 G25 H24 M_A_DQ26
3 (7,8) M_CKE1 MA_CKE1 MA0_ODT1 M_ODT1 (7,8) MB_DATA26 MA_DATA26 3
J21 U19 M_B_DQ25 E24 F22 M_A_DQ25
To SODIMM socket A (near)
To SODIMM socket B (Far)
(7,8) M_CKE0 MA_CKE0 MA0_ODT0 M_ODT0 (7,8) MB_DATA25 MA_DATA25
M_B_DQ24 E23 F20 M_A_DQ24
(7,8) M_A_A[0..15] MB_DATA24 MA_DATA24
M_A_A15 K19 J25 M_B_A15 M_B_DQ23 C24 C23 M_A_DQ23
MA_ADD15 MB_ADD15 M_B_A[0..15] (7,8) MB_DATA23 MA_DATA23
M_A_A14 K20 J26 M_B_A14 M_B_DQ22 B24 B22 M_A_DQ22
M_A_A13 MA_ADD14 MB_ADD14 M_B_A13 M_B_DQ21 MB_DATA22 MA_DATA22 M_A_DQ21
V24 MA_ADD13 MB_ADD13 W25 C20 MB_DATA21 MA_DATA21 F18
M_A_A12 K24 L23 M_B_A12 M_B_DQ20 B20 E18 M_A_DQ20
M_A_A11 MA_ADD12 MB_ADD12 M_B_A11 M_B_DQ19 MB_DATA20 MA_DATA20 M_A_DQ19
L20 MA_ADD11 MB_ADD11 L25 C25 MB_DATA19 MA_DATA19 E20
M_A_A10 R19 U25 M_B_A10 M_B_DQ18 D24 D22 M_A_DQ18
M_A_A9 MA_ADD10 MB_ADD10 M_B_A9 M_B_DQ17 MB_DATA18 MA_DATA18 M_A_DQ17
L19 MA_ADD9 MB_ADD9 L24 A21 MB_DATA17 MA_DATA17 C19
M_A_A8 L22 M26 M_B_A8 M_B_DQ16 D20 G18 M_A_DQ16
M_A_A7 MA_ADD8 MB_ADD8 M_B_A7 M_B_DQ15 MB_DATA16 MA_DATA16 M_A_DQ15
L21 MA_ADD7 MB_ADD7 L26 D18 MB_DATA15 MA_DATA15 G17
M_A_A6 M19 N23 M_B_A6 M_B_DQ14 C18 C17 M_A_DQ14
M_A_A5 MA_ADD6 MB_ADD6 M_B_A5 M_B_DQ13 MB_DATA14 MA_DATA14 M_A_DQ13
M20 MA_ADD5 MB_ADD5 N24 D14 MB_DATA13 MA_DATA13 F14
M_A_A4 M24 N25 M_B_A4 M_B_DQ12 C14 E14 M_A_DQ12
M_A_A3 MA_ADD4 MB_ADD4 M_B_A3 M_B_DQ11 MB_DATA12 MA_DATA12 M_A_DQ11
M22 MA_ADD3 MB_ADD3 N26 A20 MB_DATA11 MA_DATA11 H17
M_A_A2 N22 P24 M_B_A2 M_B_DQ10 A19 E17 M_A_DQ10
M_A_A1 MA_ADD2 MB_ADD2 M_B_A1 M_B_DQ9 MB_DATA10 MA_DATA10 M_A_DQ9
N21 MA_ADD1 MB_ADD1 P26 A16 MB_DATA9 MA_DATA9 E15
M_A_A0 R21 T24 M_B_A0 M_B_DQ8 A15 H15 M_A_DQ8
MA_ADD0 MB_ADD0 M_B_DQ7 MB_DATA8 MA_DATA8 M_A_DQ7
A13 MB_DATA7 MA_DATA7 E13
K22 K26 M_B_BS#2 (7,8) M_B_DQ6 D12 C13 M_A_DQ6
(7,8) M_A_BS#2 MA_BANK2 MB_BANK2 MB_DATA6 MA_DATA6
R20 T26 M_B_BS#1 (7,8) M_B_DQ5 E11 H12 M_A_DQ5
(7,8) M_A_BS#1 MA_BANK1 MB_BANK1 MB_DATA5 MA_DATA5
T22 U26 M_B_BS#0 (7,8) M_B_DQ4 G11 H11 M_A_DQ4
(7,8) M_A_BS#0 MA_BANK0 MB_BANK0 MB_DATA4 MA_DATA4
M_B_DQ3 B14 G14 M_A_DQ3