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5 4 3 2 1
MS-6717 V.100
CONTENT PAGE
D
Cover Page 1 D
Block Diagram 2
Clock Gen.& Clock Buffer 3-4
CPU: AMD Socket-462 Processor AMD Socket A 5-6
SiS 746 Host / AGP 7
Chipset: SIS 746 SiS 746 Memory 8
SIS 963 SOUTH BRIDGE 746 MuTiol/Other 9
746 POWER 10
LPC I/O: W83697HF SIS 963 11-14
C
AC'97 CODEC:Realtek ALC650 DDR SLOT 1-3 15-16
C
DDR Termination 17
Expansion: PCI Slot * 5 AGP Slot 18
PCI slot 1~6 19-21
LAN PHY(RTL8201) & RJ45 22
IDE Connector 23
MSI Power On / Suspend LED State USB connector 24
BIOS S0 S1/S3 S5
Single Green Off Off
KB/MS Connector 25
Color
AC'97 CODEC 26
Dual Green Red Off
Color Audio Connector 27
Green: MSI_LED1=' 1' MSI_LED2=' 0' LPC I/O W83697HF 28
B Red : MSI_LED1=' 0' MSI_LED2=' 1' B
Single Color S1/S3 status: Flash & FAN & H/WMonitor 29
MSI_LED1=' 0' MSI_LED2=' 1'
Parallel Port 30
Serial Port 31
MSI ACPILED & VDIM state PWM ST6911D 32
BIOS S0 S1/S3 S5
ACPI Contorller 33
Single ACPILED:Low ACPILED:Hi & VDIM:Hi ACPILED:Hi-z
Color VDIM :Hi VDIM :Low Front Panel&ATX power CONN. 34
Dual ACPILED:Low ACPILED:Hi & VDIM:Hi ACPILED:Hi-z SCREW MENU 35
Color VDIM :Hi VDIM :Low
Note :
1). 1Hz means Blinking frequence of ACPILED signal.
2). VDIM is no voltage in S5 state.
A A
MICRO-STAR INT'L CO.,LTD.
Title
COVER SHEET
Size Document Number Rev
MS-6717 0B
Custom
Date: Wednesday, November 06, 2002 Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1
MS-6717 Block Diagram
D
K7 462-Pin Socket Processor Clock D
VRM 9.0
FWDCLK_DDR from SiS740
CPUCLK
CPUCLK#
ADDR(In-Out)
PWR-MNG
DATA
INT & PWR-MNG
APICCLK0
DDRCLK-[0..5]
DDRCLK[0..5]
AGP SLOT SIS746
3 DDR
740CCLK
C 740DCLK C
Modules
Hyper Zip
ZCLK0 PC2700
ZCLK1
PCI 2.2
UltraDMA
IDE Primary 33/66/100
IDE Secondary
PCI Conn 1
PCI Conn 2
PCI Conn 3
PCI Conn 4
PCI Conn 5
PCI CNTRL
USB Port 1 SIS963 PCI ADDR/DATA
USB Port 2 USB
APICCLK1
USB Port 3
B B
961PCLK
USB Port 4
OSCI
USB Port 5
LPC
USB Port 6
Onboard
AC'97 Link
WINBOND
AC'97 Codec
W83697HF
Floopy Parallel
SIOPCLK
SIO24M
A A
I/O set to 48MHz Serial
MICRO-STAR INT'L CO.,LTD.
Title
BLOCK DIAGRAM
Size Document Number Rev
MS-6717 0B
Custom
Date: Wednesday, November 06, 2002 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1
CP27
X_COPPER CLK2
VCC3 L36 CLOCK GEN (746) By-Pass Capacitors Place near to the Clock Buffer
D 1 2 CLK3_3V 1 D
VDDREF
11 VDDZ
13 VDDPCI
120S_0805 19 100:ADD 15P
C261 C247 VDDPCI 746CCLK C197 10p
0.1u
28 VDD48 100:CHANGE VALUE 10 OHM TO 33 OHM
C236 C234 0.1u 29
X_4.7U_0805 C217 0.1u C246 C248 VDDAGP CPUCLK C198 15p
0.1u 0.1u 0.1u 12 40 R147 33 CPUCLK
PCI_STOP# CPUCLK_0T CPUCLK (5)
39 R148 33 CPUCLK# CPUCLK# C199 15p
CPUCLK_0C CPUCLK# (5)
5 43 R145 0 746CCLK
GNDREF CPUCLK_1T 746CCLK (7)
8 APICCLK0 C201 10p
GNDZ
18 GNDPCI 10A:CHANGE VALUE 22 OHM TO 33 OHM
24 47 R143 33 APICCLK0 APICCLK1 C202 10p
GNDPCI IOAPIC1 APICCLK0 (5)
25 46 R144 33 APICCLK1 10A:ADD 15P
GND48 IOAPIC0 APICCLK1 (12)
32 GNDAGP
31 R149 33 AGPCLK0 AGPCLK0 C204 15p
AGPCLK0 AGPCLK0 (7)
30 R150 33 AGPCLK1
AGPCLK1 AGPCLK1 (18)
AGPCLK1 C205 15p
VCC3 R146 X_1K 42 9 R166 22 ZCLK1
RESET# ZCLK0 ZCLK1 (11)
38 10 R167 22 ZCLK0 96XPCLK 7 8
VDDCPU ZCLK1 ZCLK0 (9)
CLK2_5V 48 SIOPCLK 5 6
VDDAPIC FS2 RN70 7
FS2/PCICLK_F0 14 8 33_8P4R 96XPCLK 96XPCLK (11) 3 4
41 15 FS3 5 6 SIOPCLK PCICLK1 1 2
GNDCPU FS3/PCICLK_F1 SIOPCLK (28)
C214 C229 45 16 3 4 CN23 X_8P4C-10P
0.1u 0.1u GNDAPIC PCICLK0 PCICLK1
PCICLK1 17 1 2 PCICLK1 (19)
20 7 8 PCICLK2 PCICLK2 7 8
PCICLK2 PCICLK2 (20)
21 5 6 PCICLK3 PCICLK3 5 6
PCICLK3 PCICLK3 (20)
VCC3 R25 10K 44 22 3 4 PCICLK4 PCICLK4 3 4
CPUSTOP# PCICLK4 PCICLK4 (21)
23 1 2 PCICLK5 PCICLK5 1 2
PCICLK5 PCICLK5 (21)
C RN71 33_8P4R CN24 X_8P4C-10P C
VCC3 R4 10K 33 2 FS0 R164 33 OSCI
PD# FS0/REF0 OSCI (12)
L32 3 FS1 R165 X_33 VOSCIN UCLK48M C206 10p
FS1/REF1 FS4
NC 4
1 2 CLK2_5V SIO24M C207 10p
VCC2_5 *100:ADD R4 27 R151 22 UCLK48M
48MHz UCLK48M (13)
26 MULSEL R152 22 SIO24M ZCLK1 C259 X_10p
24_48MHz SIO24M (28)
X_120S_0805
ZCLK0 C260 X_10p
CP18
pin 26 set to 48MHz
SCLK 35 SMCLK (4,12,15,16,33)
34 OSCI C257 10p
SDATA SMDATA (4,12,15,16,33)
X_COPPER
36 VOSCIN C258 X_10p
VDDA
VCC3 C203
L33
102p
1 2
37 GNDA
C200
X_120S_0805 C216
4.7U_0805 0.1u
CP20
X1
X2
FS2 R184 10K
VCC3
X_COPPER
6
7
B FS3 R170 10K B
Y1 VCC3
This pin has 120K pull down --> FS4 RN72 1 2 X_10K_8P4R
14.318MHz This pin has 120K pull down --> FS1 3 4
C235 C232 This pin has 120K pull down --> FS0 5 6
10p 10p 7 8
Default freq CPU:100/ZCLK:133/AGP:66
A A
MICRO-STAR INT'L CO.,LTD.
Title
CLOCK GEN
Size Document Number Rev
MS-6717 0B
Custom
Date: Tuesday, December 24, 2002 Sheet 3 of 36
5 4 3 2 1
8 7 6 5 4 3 2 1
Clock Buffer ( FOR 3 DDR SDRAM DIMMS )
DDRCLK[0..8]
DDRCLK[0..8] (15,16)
D D
VCC2_5
DDRCLK#[0..8]
DDRCLK#[0..8] (15,16)
VCC2_5
C80 C95 C94 L13 CP5 CBVDD CLK1
ICS 93735
33p 103p 33p
X_80-0805 X_COPPER CBVDD 15 VDDI2C By-Pass Capacitors
4 VDD
11 Place near to the Clock Buffer
VDD
21 VDD
28 VDD
34 VDD
38 DDRCLK8 C136 X_10P
VDD DDRCLK8
45 VDD CLK0 3
C145 5 DDRCLK5 DDRCLK5 C137 X_10P
CLK1 DDRCLK2
10u-0805 CLK2 10
20 DDRCLK6 DDRCLK2 C140 X_10P
CLK_BUF_AVDD CLK3 DDRCLK3
16 AVDD CLK4 22
46 DDRCLK0 DDRCLK6 C142 X_10P
C122 C123 CLK5 DDRCLK7
CLK6 44
39 DDRCLK4 DDRCLK3 C143 X_10P
0.1uF 0.01uF CLK7 DDRCLK1
CLK8 29
17 27 DDRCLK0 C57 X_10P
AGND CLK9
C (3,12,15,16,33) SMCLK
SMCLK 12 2 DDRCLK#8 DDRCLK7 C58 X_10P C
SMDATA SCLK CLK#0 DDRCLK#5
(3,12,15,16,33) SMDATA 37 SDATA CLK#1 6
9 DDRCLK#2 DDRCLK4 C61 X_10P
SDCLKO_DDR CLK#2 DDRCLK#6
(8) SDCLKO_DDR 13 CLK_IN CLK#3 19
23 DDRCLK#3 DDRCLK1 C64 X_10P
CLK#4 DDRCLK#0
CLK#5 47
43 DDRCLK#7
CLK#6 DDRCLK#4
CLK#7 40
30 DDRCLK#1
CLK#8
CLK#9 26
14 DDRCLK#8 C135 X_10P
CLK_IN# BFB_OUT R55 22 FB_OUT
FB_OUT 33
FB_OUT 35 32 DDRCLK#5 C138 X_10P
FB_IN FB_OUT#
DDRCLK#2 C139 X_10P
DDRCLK#6 C141 X_10P
DDRCLK#3 C144 X_10P
36 FB_IN# DDRCLK#0 C56 X_10P
GND DDRCLK#7 C59 X_10P
GND
GND
GND
GND
GND
GND
GND
GND
GND
18 DDRCLK#4 C60 X_10P
24
25
31
41
42
48
DDRCLK#1 C63 X_10P
1
7
8
B B
FB_OUT C62 10pF
CP4
VCC2_5 CBVDD
X_COPPER
L12 X_80-0805 CBVDD
VCC5
C121 U4 VCC2_5
C148 C124 0.1uF C103 YLT1087S-SOT89-0.8A
EC16 0.1uF EC14 0.01uF C65 0.1uF 3
C147 0.1uF C106 C66 VIN VOUT 2
X_22u 0.01uF X_22u 0.1uF 0.1uF R92 C111 EC15
200 X_0.1u 47u
C150 1
0.1u ADJ
C151 R103
X_0.1u 200
A A
*100:NO STUFF
MICRO-STAR INT'L CO.,LTD.
Title
CLOCK BUFFER
Size Document Number Rev
MS-6717 0B
Custom
Date: Monday, December 23, 2002 Sheet 4 of 36
8 7 6 5 4 3 2 1
5 4 3 2 1
CPU FERR BLOCK
AMD 462PGA Socket - Signals SADDINCLK#
SADDINCLK# (7)
VCC3
SDATAINCLK#0
SDATAINCLK#[0..3] (7)
CPU1A SDATAINCLK#1
SDATA#0 AA35 AE1 A20M# SDATAINCLK#2 V_CORE R47
(7) SDATA#[0..63] SDATA0 A20M A20M# (6,12) 510
SDATA#1 W37 AG1 FERR SDATAINCLK#3
SDATA#2 SDATA1 FERR HINIT#
W35 SDATA2 INIT AJ3 HINIT# (6,12)
SDATA#3 Y35 AL1 INTR
SDATA3 INTR INTR (6,12)
SDATA#4 U35 AJ1 IGNNE# R41
SDATA4 IGNNE IGNNE# (6,12) 680 FERR# (12)
SDATA#5 U33 AN3 NMI
SDATA5 NMI NMI (6,12)
SDATA#6 S37 AG3 CPURST#
SDATA6 RESET CPURST# (7)
D SDATA#7 S33 AN5 SMI# C D
SDATA7 SMI SMI# (6,12)
SDATA#8 AA33 AC1 STPCLK# FERR B Q12
SDATA8 STPCLK STPCLK# (6,12)
SDATA#9 AE37 CPU_PWOK E 2N3904
SDATA#10 SDATA9 CPU_PWOK C37
AC33 SDATA10 PWROK AE3 CPU_PWOK (33)
SDATA#11 AC37 X_33p
SDATA11