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ZZZ1

LA-6741P
DA60000JE10

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Brazos PCM10 LA6741 Schematics Document

AMD APU Ontario-FT1+ FCH Hudson-M1

2010-11-30
3 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2010/05/06 Deciphered Date Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Tuesday, November 30, 2010 Sheet 1 of 36
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A B C D E

Compal Confidential
Model Name : Brazos
File Name : LA6741
DDR3-SO-DIMM X2
1 Single Channel BANK 0, 1, 2, 3
1

page 7,8
DDR3-800/1066(1.5V)
DDR3-800/1066(1.35V)
LVDS Conn. AMD FUSION APU
page 11 Ontario FT1
BGA-413 PCI-Express
page4~6

HDMI
page 9 MINI Card LAN(10/100)
WLAN RTL8105E-VC-GR
page 19 page 18

UMI*8
2
CRT 2

page 10
RJ45
page 18

Bluetooth CMOS Camera USB conn x3
AMD HUDSON-M1 page 18 page 11 page 24

605-BALL
Internal 3.3V 48MHz USB
S-ATA clock GEN
page12~16

HDA Codec port 0 3.3V 24.576MHz/48Mhz
ALC259-GR HD Audio
page 20 Card Reader
RTS5138
3 S-ATA HDD LPC BUS page 17 3

Conn.page 17
SPK
CONN 3 in 1
page 21
RTC CKT. socket
page 13
EC page 17

ENE KB926D3
Power/B page 22
Power On/Off CKT. page 23
page 24

USB I/O Conn. Int.KBD
DC/DC Interface CKT. Touch Pad page 23
page 24
page 23
page 25
4
BIOS 4
page 23
Power Circuit DC/DC Debug port
page 19
page 26,28,29
30,31,32,33
Security Classification Compal Secret Data Compal Electronics,Ltd.
2010/05/06 Title

CHARGER LED Issued Date Deciphered Date
MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 27 page 21 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 2 of 36
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DDR3 Voltage Rails
1
FCH SM Bus0 address FCH SM Bus1 address 1

Device HEX Address Device HEX Address
SDDIM I A0 1010 0000 WLAN
+5VS
power SDDIM II A2 1010 0010
plane +3VS
+1.5VS
+5VALW +CPU_CORE
EC SM Bus1 address EC SM Bus2 address
+B +1.5V +NB_CORE
+3VALW +1.8VS Device HEX Address Device HEX Address
+3VL
+0.75VS Smart Battery 16H 0001 011X b APU internal themal sensor 1001 100X b
State +5VL +1.1VALW +1.1VS
+1.0VS
+RTCVCC

S0
2 O O O O POWER CPU SDDIM 2

SOURCE PLAN HDMI LVDS CRT FCH CORE I/II WLAN BATT APU
S1
O O O O
TDP1_AUXP
APU +3VS V
S3
O O O X TDP1_AUXN

LTDP0_AUXP V
S5 S4/AC
O O X X LTDP1_AUXN
APU +3VS
+5VS
S5 S4/ Battery only DAC_SCL
O X X X APU +3VS
V
DAC_SDA +5VS
S5 S4/AC & Battery
don't exist X X X X SIC
V
APU +3VS
SID +3VALW
SVC
APU +1.8VS V
SVD

SMB_FCH_CK0
3
FCH +3VS V 3
@ Reserve SMB_FCH_DA0

SMB_FCH_CK1
CONN@ ME CONNECTOR FCH +3VALW V
SMB_FCH_DA1

8105E@ 100M LAN function SMB_EC_CK1
EC +5VALW V
SMB_EC_DA1

8111E@ GLAN function SMB_EC_CK2
EC +3VS V
SMB_EC_DA2
REAL@ ALC259-GR

VIA@ V1802T

ROM@ not support flash ROM

FROM@ Support flash ROM
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/05/06 Deciphered Date Title
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 3 of 36
A B C D E
A B C D E

POWER SEQUENCE
POWER MAP
+3VL
VIN
1
B+ +5VL 1
B+
UP618CQAG +3VALW
+3VL
+5VALW
+3VALW,+5VALW
SUSP#
+1.1VALW
+1.8VS
SY8033BDBC ON/OFFBTN# NOTE1
T1>10ms, +3VALW to RSMRST#
SUSP# T1
EC->FCH EC_RSMRST#
+5VS T2>100ms, RSMRST# to PBTN_OUT#
T2
SI4800BDY EC->FCH PBTN_OUT#
T3>100ns, PBTN_OUT# to SLP_S5#
T3
EN_WOL# FCH->EC FCH_SLP_S5#
T4>10ms, SLP_S5# to SYSON
+3V_LAN T4
EC->PWR SYSON
AP2301GN
SUSP# +1.5V
The same with SLP_S5#
+3VS
FCH->EC FCH_SLP_S3#
SI4800BDY T5>10ms, SYSON to SUSP#
T5
ENVDD EC->PWR SUSP#
2 2
+LCDVDD
+3VS,+5VS,+0.75VS
POK SI4800BDY
+1.8VS
+1.1VALW
RT8209BGQW
EC->PWR +1.1VS_ON
1.1VSON#
+1.1VS +1.1VS
T6>100ms, SUSP# to VR_ON
IRF8113PBF T6
EC->PWR VR_ON
SUSP#
+1.0VS +CPU_CORE
+CPU_CORE_NB NOTE2
STS11N3LLH5
VR_ON PWR->EC VGATE
T7>50ms, VGATE to EC_FCH_PWROK
+CPU_CORE T7
ISL6265AH EC->FCH EC_FCH_PWROK
RTZ +CPU_CORE_NB
EC->FCH KB_RST#
98ms>T7>150ms, EC_FCH_PWROK to APU_PWRGD
T8
FCH->APU APU_PWRGD
SYSON 101ms>T7>113ms, EC_FCH_PWROK to A_RST#
T9
3 FCH->DEVICE A_RST# 3
+1.5V
RT8209BGQW
SUSP# FCH->APU LDT_RST#
+1.5VS
SI4800BDY NOTE1: RSMRST# rise time(10% to 90%)<50ms
fail time<1ms
SUSP
+0.75VS
VDTT11V8 NOTE2: EC_FCH_PWROK rise time(10% to 90%)<50ms
fail time<1ms

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2010/05/06 Deciphered Date Title
Powe map and sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 4 of 36
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5 4 3 2 1

+1.8VS

TEST_33_H C1 1 2 0.1U_0402_16V4Z R5 1 2 51_0402_1%
R74 2 1 1K_0402_5% TEST_35

R1 1 2 1K_0402_5% APU_LDT_STP# U1B TEST_33_L C2 1 2 0.1U_0402_16V4Z R9 1 2 51_0402_1%

R2 2 1K_0402_5% APU_SVC R8 2 150_0402_1%

DISPLAYPORT 1
1 <10> HDMI_TX2+ A8 H3 1

DP MISC
TDP1_TXP0 DP_ZVSS
<10> HDMI_TX2- B8 TDP1_TXN0
R3 1 2 1K_0402_5% APU_SVD G2
DP_BLON ENBKL <12>
<10> HDMI_TX1+ B9 TDP1_TXP1 DP_DIGON H2 ENVDD <12>
R4 1 2 300_0402_5% LDT_RST# <10> HDMI_TX1- A9 H1
TDP1_TXN1 DP_VARY_BL INV_PWM <12>
R6 1 2 300_0402_5% APU_PWRGD <10> HDMI_TX0+ D10 TDP1_TXP2
<10> HDMI_TX0- C10 TDP1_TXN2 TDP1_AUXP B2 HDMI_SCL <10>
D R7 1 2 510_0402_1% TEST_25_L C2 D
TDP1_AUXN HDMI_DAT <10>
<10> HDMI_CLK+ A10 TDP1_TXP3
R333 1 2 1K_0402_5% TEST_36 B10 C1
<10> HDMI_CLK- TDP1_TXN3 TDP1_HPD HDMI_HPD <10>

<12> LVDS_TX2+ B5 LTDP0_TXP0 LTDP0_AUXP A3 LVDS_SCL <12> +5VS

DISPLAYPORT 0
+3VS <12> LVDS_TX2- A5 LTDP0_TXN0 LTDP0_AUXN B3 LVDS_DAT <12> 1A
D6 D3 R10 2 1 100K_0402_5% C3
<12> LVDS_TX1+ LTDP0_TXP1 LTDP0_HPD
C6 10U_0805_10V4Z 1 2
<12> LVDS_TX1- LTDP0_TXN1
DAC_RED C12 CRT_R <11>
R64 1 2 1K_0402_5% APU_ALERT#_R A6 D13 R12 1 2 150_0402_1%
<12> LVDS_TX0+ LTDP0_TXP2 DAC_REDB
B6 A12 U2
<12> LVDS_TX0- LTDP0_TXN2 DAC_GREEN CRT_G <11>
R14 1 2 1K_0402_5% APU_PROCHOT B12 R13 1 2 150_0402_1% 1 9
DAC_GREENB VEN Thermal Pad
D8

VGA DAC
<12> LVDS_CLK+ LTDP0_TXP3 DAC_BLUE A13 CRT_B <11> 2 VIN GND 8
@ R16
@R16 1 2 1K_0402_5% APU_SIC C8 B13 R15 1 2 150_0402_1% +VCC_FAN1 3 7
<12> LVDS_CLK- LTDP0_TXN3 DAC_BLUEB VO GND
<23> EN_FAN1 4 VSET GND 6
@ R17
@R17 1 2 1K_0402_5% APU_SID V2 E1 1 5
<14> CLK_APU CLKIN_H DAC_HSYNC CRT_HSYNC <11> GND
V1 E2 C4
<14> CLK_APU# CLKIN_L DAC_VSYNC CRT_VSYNC <11>
R18 1 2 4.7K_0402_5% HDMI_DAT G996RD1U_TDFN8_3X3

CLK
<14> CLK_APU_DP D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <11>
R19 HDMI_SCL 2
1 2 4.7K_0402_5% <14> CLK_APU_DP# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <11>
10U_0805_6.3V6M

R21 1 2 4.7K_0402_5% LVDS_DAT <34> APU_SVC J1 D12 R20 1 2 499_0402_1%
SVC DAC_ZVSS
<34> APU_SVD J2 SVD

SER
R22 1 2 4.7K_0402_5% LVDS_SCL R1 TEST_4 PAD T1
APU_SIC TEST4 TEST_5
P3 SIC TEST5 R2 PAD T2
APU_SID P4 R6
SID TEST6 TEST_14
TEST14 T5 PAD T4
<14> LDT_RST#
R23 0_0402_5% 1 2 LDT_RST#_R T3 RESET_L TEST15 E4 TEST_15
<14> APU_PWRGD
R24 0_0402_5% 1 2 APU_PWRGD_R T4 K4 TEST_16 PAD T5

CTRL
@ R35
@R35 0_0402_5% PWROK TEST16 TEST_17
<14> APU_PROCHOT_FCH# 1 2 TEST17 L1 PAD T6
<23> APU_PROCHOT_EC# R45 1 2 0_0402_5% APU_PROCHOT U1 L2 TEST_18
APU_THERMTRIP#_R PROCHOT_L TEST18 TEST_19
U2 M2

TEST
THERMTRIP_L TEST19
<13> APU_ALERT#
R63 0_0402_5%1 2APU_ALERT#_R T2 ALERT_L TEST25_H K1 TEST_25_H
K2 TEST_25_L
APU_TDI TEST25_L TEST_28_H
N2 TDI TEST28_H L5 PAD T7
APU_TDO N1 M5 TEST_28_L PAD T9
R26 TEST_18 APU_TCLK TDO TEST28_L TEST_31 +3VS
2 1 1K_0402_5% P1 M21

JTAG
C TCK TEST31 PAD T8 C
APU_TMS P2 J18 TEST_33_H @ C6
R27 TEST_19 APU_TRST# TMS TEST33_H TEST_33_L
2 1 1K_0402_5% M4 TRST_L TEST33_L J19 1 2

1
DBRDY M3 U15 TEST_34_H PAD T10
R28 TEST_25_H DBREQ# DBRDY