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1 2 3 4 5 6 7 8
BOM MARK
E@ EXT VGA POPULATE
I@ INV VGA POPULATE
LE4 BLOCK DIAGRAM 1
F@ FIR MODULE POPULATE
4@ 4401 10/100M POPULATE CPU THERMAL Yonah /Calistoga /ICH-7m
5@ 5788 1G POPULATE SENSOR
VGA NVIDA CPU Yonah/Merom PG 5 14.318MHz
A SYSTEM POWER MAX1993 A
G72M (64 Bit B/W) 31W/35W CPUCLK,
CPUCLK#
(1.2V/NB_CORE/1.25V)
PG 41
16M*16(128MB) (478 Micro-FCPGA)
CLOCK GEN
(Bank*4) PG 4,5 IDTXXX/ ICSXXXX
PG 18,19,20,21 SBLINKCLK, SBLINKCLK# CPU CORE MAX8771
56pins
NBSRCCLK, NBSRCCLK#
POWER VCORE 1.2V /44A
HyperThansport I/O BUS PG 38
16X PCI-E Link 16x16 HTREFCLK
PG 3
SYSTEM MAX8734
EXT_CRT
OSC14M
POWER(3/5V)
PG 39
CRT port EXT_LVDS NORTH BRIDGE
PG 23
SWITCH EXT_TV-OUT Calistoga SYSTEM POWER MAX8632
DDRII DDRII-SODIMM1
LCD Panel INT_CRT 266,333 MHz (1.8VSUS/0.9V SMDDR_VREF)
PG 22 CIRCUIT 945GM / 945PM / 940GML
DDRII PG 16,17 PG 36
INT_LVDS INTEGRADED VGA FUNCTION 266,333 MHz
S-VIDEO INT_TV-OUT 1466 BGA PG 6,7,8,9,10,11 DDRII-SODIMM2 BATT CHARGER
PG 23 MAX8724
B
PG 16,17 PG 35 B
DMI LINK
32.768KHz 2X
DISCHARGE
PCI-E NBSRCCLK, NBSRCCLK# PG 40
USB PORT 0,2,6 USB 2.0
33MHZ, 3.3V PCI
PG 31
ICH7-M
SATA-HDD MIC IN
24.576MHz
Azalia
PG 32 652 BGA PG 28
PATA-CDROM
ATA 66/100/133 LAN
CARDREADER / IEEE 1394
PG 32 BCM4401/5788
PG 12,13,14,15 Conexant Audio CONTROLLER/CF
TI 8412
CX20549-12
PG 33 PG 24,25
LPC PCLK_E 25MHz
32.768KHz PG 28
3.3V LPC, 33MHz
C C
AMP
Express Card x1 MDC CONN 3 IN 1 CARDBUS 1394
MAX9755 SOCKET CONN
MINI PICE CARD CARD
IO/B PC87551L USB PORT 1 PG 29 PG 27 READER SD,
CON. PG 27 SM, MS,
SIO (87383) WIRE
PG 30 PG 25 PG 25 PG 24
PG 26
SPEKER
INT_SPK IO/B PCB STACK UP
PG 29 PG 29 RJ11 RJ45
IR module FAN Touchpad Keyboard FLASH
JACK JACK LAYER 1 : TOP
PG 26 PG 31 PG 31 PG 26 PG 30 PG 24
LAYER 2 : GND
PG 34
LAYER 3 : IN1
D
LAYER 4 : VCC D
LAYER 5 : IN2
LAYER 6 : IN3
PROJECT : LE4
LAYER 7 : GND
Quanta Computer Inc.
LAYER 8 : BOT Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Wednesday, November 16, 2005 Sheet 1 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
2
Board Stack up Description
PCB Layers Voltage Rails
A A
Layer 1 TOP(Component,Other) Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
Layer 2 Ground Plane VCC_CORE Core voltage for Processor X VR_ON 0.726V~0.94V
VCCP Core voltage for CPU / NB X VR_ON
Layer 3 IN1
SMDDR_VTERM 0.9V for DDR2 Termination voltage X MAINON
Layer 4 Power Plane
RVCC1.5 X X X RVCC_ON
Layer 5 IN2
RVCC3 X X X RVCCD
Layer 6 IN3
Layer 7 Ground Plane
Layer 8 BOTTOM VCC1.5 X MAIND
VCC2.5 X MAINON
VCC3 X MAIND
Power On Sequencing Timing Diagram VCC5 X MAIND
VID 1.8VSUS X X SUSON
Tsft_star_vcc 3VSUS X X SUSD
VR_ON
Vboot Vid 5VSUS X X SUSD
Vcc-core Tboot
Tboot-vid-tr
Tcpu_up 3VPCU X X X X VL
CPU_UP
5VPCU X X X X VL
B B
Vccp 9VPCU X X X X 5VPCU
Vccp_UP Tvccp_up
Vccgmch
GMCHPWRGD Tgmch_pwrgd
ACIN POWER ON TIMING
CLK_ENABLE# ACIN
Tcpu_pwrgd Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal
IMVP4_PWRGD 5VPCU/3VPCU
VCC_CORE Core voltage for Processor X VRON
NBSWON#
GMCH_VTT Core voltage for GMCH 1.05V X MAINON
SMDDR_VTERM 0.9V for DDR II Termination voltage X MAINON
Dothan Power-up Timing PWRBTN# To ICH7 SMDDR_VREF 0.9V for DDR II Reference Voltage X MAINON
Specifications
From 87541 GMCH_1.5V X MAINON
Td
S5_ON 1.8VSUS 1.8V for DDR II voltage X X SUSON
RESET# To ICH7
+2.5V X MAINON
RSMRST#
From ICH7
3VPCU X X X X VL
SUSB#,SUSC# 3VSUS X X SUSON
+3V X MAINON
BCLK From 87541
SUSON 5VPCU X X X X VL
Tc From 87541 5VSUS X X SUSON
+5V X MAINON
MAINON
Te From 87541
PWRGOOD VSUS,VCC
From 87541
C C
VR_ON
Tf
Ta Tb VIN POWER SOURCE X X X X
VCCP/1.05V
VCC VCORE_CPU PCI DEVICE IDSEL# REQ# / GNT# Interrupts
Vcc,boot
PCI7402 AD25 REQ1# / GNT1# PIRQ B/C/D
VID[5:0] CLK_EN# To clock generator
99ms < t 214
PWROK To GMCH/other PCI device
PLTRST#\PCIRST#
VCCP
From ICH7 to CPU
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild 2ms Form GMCH to CPU
Tc=BCLK stable to PWRGOOD assertion H_CPURST#
Td=PWRGOOD to RESET# de-assertion time
Te=Vcc,boot vaild to PWRGOOD assertion time
D D
PROJECT : LE4
Quanta Computer Inc.
Size Document Number Rev
System Information 1A
Date: Wednesday, November 16, 2005 Sheet 2 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
FSC FSB FSA
1
0
0
0
1
1
CPU
100
133
SRC
100
100
PCI
33
33
Place these termination to close
CK410M. Cause those Pin-out is
for Current-Mode.
3
0 1 1 166 100 33
0 1 0 200 100 33 R199 1 2 49.9/F_4
R200 1 2 49.9/F_4
0 0 0 266 100 33 C323 33P_4 VDDA_CR R196 1
A
2 49.9/F_4 A
1 0 0 333 100 33 2 1 XIN R197 1 2 49.9/F_4
R192 1 2 33_4 14M_SIO (26)
1
1 1 0 400 100 33 <500mil
Y2 U17
37
38
1 1 1 RSVD 100 33 R188 33_4
14.318MHZ 50 52 14M_REF 1 2
VDDA
VSSA
14M_ICH (14)
2
C324 33P_4 BG614318081 XTAL_IN REF RP34
1
1
2 1 XOUT 49 44 R_HCLK_CPU 4 3
XTAL_OUT CPU0 CLK_CPU_BCLK (4)
43 R_HCLK_CPU# 2 1 4P2R-S-33 C366 C361
CPU0# CLK_CPU_BCLK# (4)
RP39 *10P_4 *10P_4
2
2
CLK_EN# 10 41 R_HCLK_MCH 4 3
(14,37) CLK_EN# VTT_PWRGD#/PD# CPU1 CLK_MCH_BCLK (6)
(14) PM_STPPCI# PM_STPPCI# 55 40 R_HCLK_MCH# 2 1 4P2R-S-33
PCI_STOP# CPU1# CLK_MCH_BCLK# (6)
(14) PM_STPCPU# PM_STPCPU# 54 RP43
TI_CLK48M R195 1 CPU_STOP# R_PCIE_VGA CLK_PCIE_VGA
(25) TI_CLK48M 2 10_4 CPU2_ITP/SRC7 36 4 3 CLK_PCIE_VGA (18)
CLKUSB_48 R190 1 2 10_4 35 R_PCIE_VGA# 2 1 CLK_PCIE_VGA#
(14) CLKUSB_48 CPU2#_ITP/SRC7# CLK_PCIE_VGA# (18)
4P2R-S-33
SMbus address D2 CGCLK_SMB 46 CK-410M 33
CGDAT_SMB SCLK SRC6
47 SDATA SRC6# 32
(4,7) CPU_MCH_BSEL0 R193 1 2 8.2K/F_4 FSA 12 31 R_MCH_3GPLL RP47
4 3 CLK_MCH_3GPLL
FSA/USB_48 SRC5 CLK_PCIE_3GPLL (7)
(4,7) CPU_MCH_BSEL1 FSB 16 30 R_MCH_3GPLL# 2 1 CLK_MCH_3GPLL#
FSB/TEST_MODE SRC5# CLK_PCIE_3GPLL# (7)
R184 1 2 8.2K/F_4 FSC 53 4P2R-S-33
LE4 A: (4,7) CPU_MCH_BSEL2 FSC/TEST_SEL
SRC4 26 R_PCIE_SATA RP48
2 1 CLK_PCIE_SATA
CLK_PCIE_SATA (12)
Changed new function VDDREF_CR 48 27 R_PCIE_SATA# 4 3 CLK_PCIE_SATA#
VDD_REF SRC4# CLK_PCIE_SATA# (12)
CLKVDD 42 4P2R-S-33
VDD_CPU R_PCIE_ICH RP44 CLK_PCIE_ICH
Solved sometimes can't power on SRC3 24 2 1 CLK_PCIE_ICH (13)
CLKVDD1 1 25 R_PCIE_ICH# 4 3 CLK_PCIE_ICH#
VDD_PCI_1 SRC3# CLK_PCIE_ICH# (13)
+3VRUN 7 4P2R-S-33
VDD_PCI_2 R_PCIE_MINI RP40 CLK_PCIE_MINI
22 2 1
LE4 B: CLKVDD 21 VDD_SRC0
SRC2
SRC2# 23 R_PCIE_MINI# 4 3 CLK_PCIE_MINI#
CLK_PCIE_MINI (27)
CLK_PCIE_MINI# (27)
28 4P2R-S-33
VDD_SRC1
1
B Add R566 34 VDD_SRC2 SRC1 19 B
R566 pull high 20
VDD48_CR SRC1# RP37
10K_4 with FSA 11 VDD_48
17 R_DREFSSCLK 2 1 DREFSSCLK
SRC0 DREFSSCLK (7)
1 2 IREF 39 18 R_DREFSSCLK# 4 3 DREFSSCLK# 0816a
DREFSSCLK# (7)
2
FSA R201 475/F_4 IREF SRC0# I@4P2R-S-33
5 R_PCLK_LAN R186 1 2 33_4 PCLK_LAN
PCI5 PCLK_LAN (33)
Iref=5mA, 4 R_PCLK_LPC R181 1 2 33_4 PCLK_LPC
PCI4 PCLK_LPC (26)
1
I@4P2R-S-33 3 R_PCLK_LPC_DEBUG R178 1 2 33_4 PCLK_LPC_DEBUG
GND_PCI_1
GND_PCI_2
Ioh=4*Iref PCI3 PCLK_LPC_DEBUG (27)
GND_SRC
GND_CPU
GND_REF
R567 4 3 R_DOT96 14 56 R_PCLK_PCM R182 1 2 33_4 PCLK_PCM
(7) DOT96 DOT96 PCI2 PCLK_PCM (24)
GND_48
*10K_4 2 1 R_DOT96# 15 9 R_PCLK_SIO R194 1 2 33_4 PCLK_541
(7) DOT96# DOT96# PCIF1 PCLK_541 (30)
+3VRUN 8 PCIF0
RP35 PCIF0/ITP_EN
1 2 +3VRUN
2
R189 *10K_4 PCIF1
1 2 1:100 Mhz
13
51
2
6
29
45
2
4
CT_0505: Change footprint to ICS954206AGLFT R183 10K_4 0:96
RP33 250mA ( MAX. )
TSSOP56-8_1-5 from PCLK_ICH
Mhz
Connect 4P2R-S-10K Connect DDR R185 1 2 33_4 PCLK_ICH (13)
ICH6 Module's TSSOP56-240
2
Q32
SMB SMB
1
3
PDAT_SMB 3 1 CGDAT_SMB Tie to VCC