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5 4 3 2 1
400 Rev: A.0 15-F66-010010
Digitally signed by fdsf
DN: cn=fdsf, o=fsdfsd,
AC/BATT
CONNECTOR 31
DC/DC
CPU VR DIMM PWR CLOCK
ou=ffsdf,
Dothan/Banias
D email=fdfsd@fsdff, D
ACCELEROMETER
Gen.
ECVCC
15
BATT
(478 Micro-FCPGA)
4,5
15,34 33 32 3
c=US
LIGHT SENSOR
CHARGER 31
LCD Connector
Date: 2010.01.06
4X(133MHz/100MHz)
VCC3
25
LVDS
13
06:14:13 +07'00'
VCCP
DDRII-SODIMM0/1+1.8V_DIMM 400/533/667 MHz DDRII RC410MB
+1.8V_DIMM
707FCBGA
VTT VGA1.2V TVOUT S-Video
11,12 PCIE1.2V 24
VCC1.8V
VGA CRT
6,7,8,9,10
24
A-Link Interface
USB2.0 +5VAUX
7 Ports
24,28
33MHz PCI REALTEK
C IDE1 +3VAUX 8110S
+3VAUX
(VDD25)
RJ45/Magnetics
C
HDD 29 SB450MB 24
+1.8VAUX CARDBUS/1394/ PCMCIA (VDD18)
MINI-PCI
IDE0 564FCBGA VCC3 CARD READER CON. Wireless LAN 23
CD-ROM 29 VCC1.8V RICOH R5C841 +3VAUX +3VAUX
+3VAUX
HD VCCP +5VAUX VCC3
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VCC3
16,17,18,19,20 22 VCC5
21
25
AUDIO MDC
VCC3 CARD READER
VCC5 24 +3VAUX
26,27 30
VCC5
FAN 1
ENE 3910 14
(MicroP) ECVCC
14
B VCC5 VCC5 ECVCC
B
Touchpad Keyboard FLASH
14 14 14
Page 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
Rev. A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0
2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/
Data
07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11
Page 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A A
Rev. A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0 A.0
2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/ 2005/
Data
07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11 07/11
Elitegroup Computer Systems
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
400-1-4-01 A.0
Date: Monday, July 11, 2005 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
D Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal D
12VOUT X X X X
3V_591 X X X X
5VPCU X X X X
+3V_S5 X X X X S5_ON
+1.5V_S5 X X X X S5_ON
+1.8VSUS X X SUSON
+3VSUS X X SUSON
+5VSUS X X SUSON
+0.9VSUS DDR Termination voltage X X SUSON
CPU_CORE Core voltage for Processor X VR_ON
+0.9V X MAINON
+VCCP 1.05V rail for Processor I/O X MAINON
+1.5V X MAINON
+1.8V X MAINON
+2.5V X MAINON
+3V X MAINON
+5V X MAINON
+12V X MAINON
C C
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
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Giga LAN AD22 0 B
Mini-PCI AD23 1 C, D
CardBus+1394 AD24 2 E, F, G
EC SM Bus1 address
Device
Smart Battery
THERMAL SENSOR 1001 100X b
B B
SB450MB SM Bus address
Device
SODIMM 1010 000X b
Clock Gen 1101 001x b
Functions with Spread Spectrum Capibility for Clock
Memory
LVDS
Host Bus
PCIE Interface
A A
Elitegroup Computer Systems
Title
SYSTEM INFO
Size Document Number Rev
Custom 400-1-4-01 A.0
Date: Monday, July 11, 2005 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1
VCC3
CLK_VDD
SL18 SL17 CLK_VDD_USB
1 2 0.1uF/10V_X7R 0.1uF/10V_X7R 0.1uF/10V_X7R 2 1 VCC3
FCM2012V-121RC10-0805 FCM1608K-151T06 SL14
1
1
1
1
1
1
1
1
1
CLK_VDDA 1 2
+ SC131 SC103 SC105 SC126 SC127 SC108 SC107 SC104 SC130 FCM2012V-121RC10-0805
1
0.1uF/10V_X7R
2
2
2
2
2
2
2
2
22uF/10V_B SC106 SC95
2
22uF/16V_B
2
0.1uF/10V_X7R 0.1uF/10V_X7R 0.1uF/10V_X7R 0.1uF/10V_X7R
D 0.1uF/10V_X7R D
NBCLK# 9
CLK_VDD NBCLK 9
1- PLACE ALL THE SERIES TERMINATION SU8
CPUCLK# 4
RESISTORS AS CLOSE AS U300 AS POSSIBLE CPUCLK 4
45 VDDCPU VDDA 39
2- ROUTE ALL CPUCLK/#, NBCLK/# AND 35 VDD_SRC VSSA 38
ITPCLK/# AS DIFFERENT PAIR RULE CLK_VDD_USB 32 VDD_SRC1 NBCLK_R SR122 33 SR114 49.9_1%
21 VDD_SRC2 CPUT0 47
3- PUT DECOUPLING CAPS CLOSE TO U300 14 46 NBCLK#_R SR123 33 SR115 49.9_1%
VDD_SRC3 CPUC0 CPUCLK_R SR124 33 SR116 49.9_1%
POWER PIN 3 VDD_48 CPUT1 43
51 42 CPUCLK#_R SR125 33 SR117 49.9_1%
VDD_PCI CPUC1
7/11 6/23 56 VDD_REF CPUT2 41
CPUC2 40
44 VSS_CPU
36 34 SR126 33 SR118 49.9_1%
SC128 VSS_SRC SRCT0 SR127 33 SR119 49.9_1%
31 VSS_SRC1 SRCC0 33
26 VSS_SRC2 SRCST0 30
27pF/10V_NPO 20 29
VSS_SRC3 SRCSC0
15 VSS_SRC4 SRCST1 27
4
1
5 VSS_48 SRCSC1 28
49 24 SR136 33 SR138 49.9_1%
#3 NC1
NC #1
VSS_PCI SRCT1 SR137 33 SR139 49.9_1%
55 VSS_REF SRCC1 25
SRCT2 22
SY2 23
SRCC2
1 XIN SRCT3 18
3
2
14.318MHz/20p_SMD_4P 19
SRCC3
2 XOUT SRCT4 16
C SC129 17 C
SRCC4
SRCT5 12
27pF/10V_NPO 13
SRCC5
CLKREQ0 10 ALINKCLK 8
From uP--> 14 CLKEN# 6 VTTPWRGD#/PD CLKREQ1 11 ALINKCLK# 8
16,33 CPUSTP# 48 CPU_STP# SBSRCCLK 16
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50 CK410#=LOW CK410 MODE SBSRCCLK# 16
PCIF0/CK410#
4 SR134 33
USB_48 USBCLK 17
11,12,17 SCLK 7
SCLK CLK_VDD
11,12,17 SDATA 8
SDATA
9
FSC
53
REF1/FSB
IREF = VDD/(3xRR). 37 54
IREF REF0/FSA SR135
52
R215 REF2
Ioh = 6 * Iref 4.7K
(2.32mA) 475_1%
Voh = 0.7V @ 50 ohm FSC
FSB533# 8
ICS951413/RTM865T
CK410 FREQUENCY SELECT TABLE(MHZ) CLK_VDD
FSC FSB FSA CPU SRC PCI REF
BSEL2 BSEL1 BSEL0
FSA SR112 1 2 4.7K
B
1 0 1 100 100 33 14.31 B
0 0 1 133 100 33 14.31
0 1 1 166 100 33 14.31
SR121 33
SB_OSCIN 17
0 1 0 200 100 33 14.31 SR113 33
OSC14M 9
0 0 0 266 100 33 14.31
1 0 0 333 100 33 14.31
VCC3
1 1 0 400 100 33 14.31
1 1 1 Resv 100 33 14.31
2
2
SR141 SR140
10K 10K
Default ON
1
1
SCN10
16 RTC_RST# 1 8
17 LCD_ID0 2 7
Check if needed in next version --> 17 LCD_ID1 3 6
FSC 4 5 <--LOW: FSB533(DEFAULT), HIGH: FSB400
diptrs_fhds-04_dip-sw
OFF___ON
A A
Elitegroup Computer Systems
Title
CLK GEN.
Size Document Number Rev
Custom 400-1-4-01 A.0
Date: Monday, July 11, 2005 Sheet 3 of 35
5 4 3 2 1
5 4 3 2 1
HD#[0..63]
SU2A HD#[0..63] 6
HA#[3..31]
D 6 HA#[3..31] HA#3 HD#0 D
P4 A3# D0# A19
HA#4 U4 A25 HD#1
HA#5
HA#6
V3
A4#
A5#
Dothan D1#
D2# A22 HD#2
HD#3
R3 A6# D3# B21
HA#7 V2 A24 HD#4 VCC3 VCC3
HA#8 A7# D4# HD#5
W1 A8# 1 OF 3 D5# B26
HA#9 T4 A21 HD#6
A9# D6#
2
1
HA#10 W2 B20 HD#7
HA#11 A10# D7# HD#8 SC74
Y4 A11# D8# C20
HA#12 Y1 B24 HD#9 0.1uF/10V_X7R
A12# D9#
2
HA#13 U1 D24 HD#10 SR90
HA#14 A13# D10# HD#11 10K
AA3 A14# D11# E24
1
HA#15 Y3 C26 HD#12 SU3
HA#16 A15# D12# HD#13
AA2 A16# D13# B23 14,15 SMB_CLK3
8 SMCLK VDD 1
HA#17 AF4 E23 HD#14 THERMDA
HA#18 A17# D14# HD#15
AC4 A18# D15# C25 14,15 SMB_DAT3 7 SMDATA DXP 2
1
HA#19 AC7 H23 HD#16
HA#20 A19# D16# HD#17 SC73
AC3 A20# D17# G25 14 CPU_ALERT# 6 ALERT DXN 3
HA#21 AD3 L23 HD#18 2200pF/50V_X7R
A21# D18#
2
HA#22 AE4 M26 HD#19 5 4 THERMDC
HA#23 A22# D19# HD#20 GND OVERT
AD2 A23# D20# H24 SQ9
HA#24 AB4 F25 HD#21 F75383M
HA#25 A24# REQUEST DATA D21# HD#22 2N7002
AC6 A25# D22# G24
HA#26 AD5 PHASE PHASE J23 HD#23 VCC3 2 1 S D
A26# D23# OVERT# 14
HA#27 AE2 SIGNALS SIGNALS M23 HD#24 SR86
HA#28 A27# D24# HD#25 10K
AD6 A28# D25# J25
HA#29 AF3 L26 HD#26
A29# D26#
G
HA#30 AE1 N24 HD#27
HA#31 A30# D27# HD#28
AF1 A31# D28# M25 VCC3
H26 HD#29
C