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CPU
RJ6 Block Diagram 1
Yonah/Merom
478 PIN (micro FC-PGA) P3,4 14.318MHz
A FSB 667 MHz(166X4) A
LVDS LCD LVDS
P7
CLOCK GEN
UNBUFFERED ICS954310
DDRII 400/533/667 DDRII
DVI Calistoga SODIMM P2
M56
P12
945GM/PM
R/G/B CRT R/G/B
P11 1466 PIN (micro FCBGA) UNBUFFERED
DDRII 400/533/667 DDRII
37.5mm x 37.5mm
SODIMM
PCIE 16Lanes P5-10 P12
P36-40
DMI(2X, 4X)
RJ45
LAN PCIE Azalia Link
(Giga) MARVELL
B B
88E8055 P27
ICH7-M ALC260
P22
MDC Module
P19
PCI-E Mini PCIE
Intel 3945
P19
652 BGA TI-TPA6011A4 P23 RJ11
31mm x 31mm
PCI BUS P13-16
MIC. Jack Audio Jack INT.SPKR.
USB 1.1/2.0
USB 1.1/2.0
SATA
3.3V LPC,33MHZ
TPM 1.2 Sinosun SSX35ACB
USB SATA HDD P25
VT6212
TI_7411 Sil 3512 P24
C C
P35 P17-18 P34
USB*3 BAY P24
P26
Docking*3
P25
PCU
DoackingP25 NS PC87541
Felica P24
Finger P21
PCMCIA 1394 Memory Stick Pro(DUO) Print P26
P20 P17 BAY P24
Blue Tooth
P24
SD/MMC
Camera P26 P18
TOUCH PAD INT.K/B BIOS Camera LED
WWAN P24 P26 P21
ADI
HDD LED ADXL322JCP
P24
T/P SWITCH Track Point
Wireless SW
Wireless LED
D D
Bluetooth SW
Bluetooth LED QUANTA
LED COMPUTER
Power/Speep/Bat/HDD
Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. RJ6 Main Board 1A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
Date: Tuesday, April 11, 2006 Sheet 1 of 40
1 2 3 4 5
1 2 3 4 5 6 7 8
C4
CLK_XIN
CLK_VDDA
C1 C2
L1 MLB-160808-0300P-N2
VCC3
14M_ICH
HCLK_CPU
C5
RP47 1
*10P_4
2 *49.9/FX2_4
2
2
U1 10U/6.3V/X5R 0.1U_4 HCLK_CPU#
45
46
33P 3 4
Y1 R687 4.7K_4 CPU_BSEL1 HCLK_MCH RP48 1 2 *49.9/FX2_4
14.318MHZ 58 60 R2 33/F_6 14M_ICH HCLK_MCH# 3 4
VDDA
GNDA
C6 X1 [FSB] REF0 14M_ICH (15)
1
CLK_XOUT 57 52 R_HCLK_CPU RP30 1 2 10X2 HCLK_CPU CLK_PCIE_M56 RP49 1 2 *[email protected]/FX2_4
X2 CPUCLKT0 HCLK_CPU (3)
51 R_HCLK_CPU# 3 4 HCLK_CPU# CLK_PCIE_M56# 3 4
CPUCLKC0 HCLK_CPU# (3)
33P R_HCLK_MCH RP31 1
(28) CLKEN# 10 Vtt_PerGd#/PD CPUCLKT1 49 2 10X2 HCLK_MCH
HCLK_MCH (5)
CLK_PCIE_DOCK RP50 1 2 *49.9/FX2_4
62 48 R_HCLK_MCH# 3 4 HCLK_MCH# CLK_PCIE_DOCK# 3 4
(15) PM_STPCPU# CPU_STOP# CPUCLKC1 HCLK_MCH# (5)
A (15) PM_STPPCI# 63 PCI/PCIEX_STOP# A
44 R_CLK_PCIE_M56 RP32 1 2 E@22X2 CLK_PCIE_M56 CLK_PCIE_SATA RP51 3 4 *49.9/FX2_4
CPUCLKT2_ITP/PCIEXT8 CLK_PCIE_M56 (36)
54 43 R_CLK_PCIE_M56# 3 4 CLK_PCIE_M56# CLK_PCIE_SATA# 1 2
(12,15,20) PCLK_SMB SCLK CPUCLKC2_ITP/PCIEXC8 CLK_PCIE_M56# (36)
(12,15,20) PDAT_SMB 55 SDATA
CLK48_7411 R17 12.1_4 41 DREFSSCLK RP52 3 4 *[email protected]/FX2_4
(17) CLK48_7411 PREQ1#PCIEXT7 delete R544
CLK48_USB R20 12.1_4 40 DREFSSCLK# 1 2
(15) CLKUSB_48 PEREQ2#PCIEXCT7
VCCP R583 4.7K_4 12
CPU_BSEL1 R688 *0_4 FSLA/USB_48MHz [_2X] R_CLK_PCIE_DOCK RP33 1
16 FSLB/TEST_MODE[*PEREQ1#] PCIEXT6 39 2 22X2 CLK_PCIE_DOCK
CLK_PCIE_DOCK (25) SWAP DREFCLK RP53 3 4 *[email protected]/FX2_4
CPU_BSEL2 61 38 R_CLK_PCIE_DOCK# 3 4 CLK_PCIE_DOCK# DREFCLK# 1 2
REF1/FSLC/TEST_SEL PCIEXC6 CLK_PCIE_DOCK# (25)
36 R_CLK_PCIE_ICH RP40 1 2 22X2 CLK_PCIE_ICH CLK_PCIE_LAN RP54 3 4 *49.9/FX2_4
PCIEXT5 CLK_PCIE_ICH (14)
VDDREF 56 35 R_CLK_PCIE_ICH# 3 4 CLK_PCIE_ICH# CLK_PCIE_LAN# 1 2
VDDREF PCIEXC5 CLK_PCIE_ICH# (14)
L2 0_6 VCC3_CLK_VDDCPU 50
VCC3 VDDCPU
30 CLK_PCIE_ICH RP55 1 2 *49.9/FX2_4
VDDPCI PCIEXT4 CLK_PCIE_ICH#
1 VDDPCI PCIEXC4 31 SWAP 3 4
C7 C15 C11 7
0.1U_4 10U/6.3V/X5R 0.1U_4 R689 0_4 VDDPCI R_CLK_PCIE_SATA RP34 3
SATACLKT 26 4 22X2 CLK_PCIE_SATA
CLK_PCIE_SATA (13)
CLK_PCIE_MINI RP56 3 4 *49.9/FX2_4
R690 *0_4 21 27 R_CLK_PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_MINI# 1 2
VDDPCIEX [GND] SATACLKC CLK_PCIE_SATA# (13)
L3 0_6 VCC3_CLK_VDDPCIE 28
VCC3 VDDPCIEX
42 24 R_CLK_PCIE_LAN RP35 3 4 22X2 CLK_PCIE_LAN CLK_PCIE_MCH RP58 3 4 *49.9/FX2_4
VDDPCIEX PCIEXT3 CLK_PCIE_LAN (27)
25 R_CLK_PCIE_LAN# 1 2 CLK_PCIE_LAN# CLK_PCIE_MCH# 1 2
PCIEXC3 CLK_PCIE_LAN# (27)
C3 C12 C13 C14 C41
0.1U_4 0.1U_4 0.01U_4 0.1U_4 10U/6.3V/X5R 22 R_CLK_PCIE_MINI RP41 3 4 22X2 CLK_PCIE_MINI
PCIEXT2 CLK_PCIE_MINI (20)
VDD48 11 23 R_CLK_PCIE_MINI# 1 2 CLK_PCIE_MINI#
delete R45 VDD48 PCIEXC2 CLK_PCIE_MINI# (20)
PCLK_MP C16 *15P
(20) CLKREQ_MINIPCIE# 32 *PEREQ3#
33 19 R_CLK_PCIE_MCH RP57 3 4 22X2 CLK_PCIE_MCH PCLK_6212 C17 *15P
*PEREQ4# PCIEXT1 CLK_PCIE_MCH (5)
20 R_CLK_PCIE_MCH# 1 2 CLK_PCIE_MCH#
PCIEXC1 CLK_PCIE_MCH# (5)
PCLK_3512 C18 *15P
B R40 4.3K VREF 47 B
Zo=50 IREF/VREF R_DREFSSCLK RP36 3
27FIX/LCD_SSCGT/PCIEX0T 17 4 I@22X2 DREFSSCLK DREFSSCLK (5)
PCLK_7411 C21 *15P
(96MHz) RP37 I@22X2 18 R_DREFSSCLK# 1 2 DREFSSCLK#
27SS/LCD_SSCGC/PCIEX0C DREFSSCLK# (5)
DREFCLK 4 3 R_DREFCLK 14 R528 *E@100/F_4 M56_27MHZ CLK48_USB C22 *15P
(5) DREFCLK DOTT_96MHz [27FIX] M56_27MHZ (36)
DREFCLK# 2 1 R_DREFCLK# 15 R529 *E@33/F_6 M56_27MHZ# (27MHz)
(5) DREFCLK# DOTC_96MHz [27SS] M56_27MHZ# (36)
CLK48_7411 C23 *15P
M56_27MHZ R691 E@100/F_4 5 R_PCLK_MP R38 33/F_6 PCLK_MP
[PCICLK3] *SELPCIEX0_LCD#/PCICLK5 PCLK_MP (20)
M56_27MHZ# R692 E@33/F_6 4 R_PCLK_6212 R39 33/F_6 PCLK_6212 PCLK_551 C667 *15P
[PCICLK2_2X] PCICLK4 PCLK_6212 (35)
R474 12.1_4 PCLK_9630
PCLK_9630 (25)
3 R_PCLK_3512 R41 12.1_4 PCLK_3512 R578 PCLK_ICH C25 *15P
[PCICLK1_2X] PCICLK3 PCLK_3512 (34)
L5 0_6 VDDPCI 64 R_PCLK_7411 R42 33/F_6 PCLK_7411 [email protected]
VCC3 [PCICLK0_2X] **PCICLK2/REQ_SEL PCLK_7411 (17)
9 R_PCLK_ICH R43 33/F_6 PCLK_ICH PCLK_9630 C671 *15P
*SELLCD_27#/PCICLK_F1 PCLK_ICH (14)
34 8 R_PCLK_551 R452 33/F_6 PCLK_551
*PWRSAVE# [PEREQ2#] ITPEN/PCICLK_F0 PCLK_551 (21)
C8 C10 C24 R15 10K_4
0.1U_4 0.1U_4 *10U/6.3V/X5R (1.2v)
GND
GND
GND
GND
GND
GND
GND
R_PCLK_7411 R44 *10K_4
VCC3
R_PCLK_MP R4 *10K_4
R5 0_6 VDD48 * Internal pull up to VDD
53
13
59
2
6
29
37
**Internal pull down to GND R_PCLK_ICH R6 E@10K_4
ICS954310/ICS9LPR310
Recommend change size to C9 C33 ICS9LPR310 :(M56)
0603 as RJ1 from shortage 0.1U_4 0.47U SATA Spread and Frequency Selection Table
ADD R689 0 ohm Delete R690,R688,R44,R4 (SEL_SATA) :
R40 4.3K R528,R529,RP37
R7 0_6 VDDREF R691 100/F RP47,RP48,RP49,RP50 VCO 27,26 Spread
R692 33 RP51,RP52,RP53,RP54 SEL_SATA SS3 SS2 MHZ MHZ %
R687 4.7K RP55,RP56,RP58
C19 C40 1 0 0 tbd 100 -0.2 Down
0.1U_4 0.47U R528,R691 : 100/F ohm
C C
(915GM): Don't care R528,R529,R691,R692 1 0 1 tbd 100 -0.3 Down
SEL_SRC0(Pin 17,18)(R4) REQ_SEL(Pin 40,41)(R44) 1 1 0 tbd 100 -0.4 Down
LCDCLK Spread and Frequency Selection Table (SEL_LCD) :
0: LCDCLK Pair 0: PCIEXT7/PCIEXC7 1 1 1 tbd 100 -0.5 Down
1: SRCCLK0 pair 1: PREQ# Spread Spread
SEL_LCD SEL_LCD
SS3 SS2 SS1 SS0 17,18 MHZ % SS3 SS2 SS1 SS0 17,18 MHZ % Signal 945GM 945PM
SEL_LCD(Pin 17,18)(R6) IREF (Pin 39) : 1 0 0 0 0 96 +/-1.5 0 0 0 0 0 27 +/-0.25
R578 NI 71.5
0: 27MHZSS/27MHZSS# pair (M56) 475_1% : Sets the IREF current to 1 0 0 0 1 96 +/-1.25 0 0 0 0 1 27 +/-0.5
1: LCDCLK pair (945GM) 2.32mA CLK_PCIE_M56 RP32 NI 33X2
1 0 0 1 0 96 +/-1.0 0 0 0 1 0 27 +/-0.75
RP49 NI 49.9
Center
Center
1 0 0 1 1 96 +/-0.8 0 0 0 1 1 27 +/-1
R3 10K_4 CPU_BSEL2 DREFSSCLK RP36 33X2 NI
1 0 1 0 0