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First Edition (May, 1_)
The following paragraph does not apply to the United Kingdom or any country where
such provisions are Inconsistent with Iocallaw:INTERNATIONAL BUSINESS MACHINES
CORPORATION PROVIDES THIS PUBLICATION HAS IS" WITHOUT WARRANTY OF ANY
KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Some states do not allow disclaimer of express or Implied warranties In certain
transactions, therefore, this statement may not apply to you.
This publication could include technical inaccuracies or typographical errors. Changes
are periodically made to the information herein; these changes will be incorporated in
new editions of the publication. IBM may make Improvements and/or changes in the
product(s) and/or the program(s) described in this publication at any time.
It is possible that this publication may contain reference to, or information about, IBM
products (machines and, programs), programming, or services that are not announced
in your country. Such references or information must not be construed to mean that
IBM intends to announce such IBM products, programming, or services In your country.
THE PUBLICATION OF THE INFORMATION CONTAINED HEREIN IS NOT INTENDED TO
AND DOES NOT CONVEY ANY RIGHTS OR LICENSES, EXPRESS OR IMPLIED, UNDER
ANY IBM PATENTS, COPYRIGHTS, TRADEMARKS, MASK WORKS OR ANY OTHER
INTELLECTUAL PROPERTY RIGHTS.
Requests for copies of this publication and for technical information about IBM
products should be made to your IBM Authorized Dealer or your IBM Marketing
Representative.
Personal System/2 Is a registered trademark of the International Business Machines
Corporation.
e Copyright International Business Machines Corporation 1988. All rights reserved.
No part of this work may be reproduced or distributed in any form or by any means
without prior permission in writing from the IBM Corporation.
Preface

The Technical Reference library is intended for those who develop
hardware and software products for IBM Personal Computers and
IBM Personal System/2. Users should understand computer
architecture and programming concepts.

This technical reference provides hardware and software interface
information for the IBM Personal System/2 Model 80 and should be
used with the following publications:
IBM Personnal Systeml2 Hardware Interface Technical Reference
IBM Personal Systeml2 and Personal Computer BIOS Interface
Technical Reference

This manual consists of the following sections:
Section 1, "System Overview," describes the system, features,
and specifications.
Section 2, "Programmable Option Select," describes registers
used for configuration.
Section 3, "System Board," describes the system-specific
hardware implementations.

Warning: The term "Reserved" describes certain signals, bits, and
registers that should not be changed. Use of reserved areas can
cause compatibility problems, loss of data, or permanent damage to
the hardware. When the contents of a register are changed, the state
of the reserved bits must be preserved. When possible, read the
register first and change only the bits that must be changed.

For information about components or devices not described in this
manual, refer to the Hardware Interface Technical Reference.
Information about diskette drives, fixed disk drives, adapters, and
external options are in separate option technical references.

III
Notes:

Iv
Contents
Section 1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
System Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
System Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1-5
System Board I/O Address Map . . . . . . . . . . . . . . . . . . . . . . 1-6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Section 2. Programmable Option Select . . . . . . . . . . . . . . . . . 2-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
POS Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Card Selected Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
System Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
System Board Enable/Setup Register (Hex 0094) ......... 2-7
System Board POS Register 2 (Hex 0102) . . . . . . . . . . . . . . 2-8
System Board POS Register 3 (Hex 0103) - Type 1 ........ 2-9
System Board POS Register 3 (Hex 0103)-Type 2 ....... 2-10
Adapter Enable/Setup Register (Hex 0096) ............ 2-12

Section 3. System Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
80387 Math Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Micro Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Matched Memory, Type 1 Implementation . . . . . . . . . . . . . . 3-3
Matched Memory, Type 2 Implementation ............. 3-12
Central Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Read-Only Memory Subsystem (Type 1) . . . . . . . . . . . . . . 3-16
Read-Only Memory Subsystem (Type 2) . . . . . . . . . . . . . . 3-16
Random Access Memory Subsystem . . . . . . . . . . . . . . . . 3-17
Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Memory Subsystem Control . . . . . . . . . . . . . . . . . . . . . . 3-19
Memory Registers - Type 1 . . . . . . . . . . . . . . . . . . . . . . 3-20
Memory Registers - Type 2 . . . . . . . . . . . . . . . . . . . . . . 3-23
System Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
System Board Memory Connectors . . . . . . . . . . . . . . . . . 3-33
Real-Time Clock/Complementary Metal-Oxide Semiconductor
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
Miscellaneous System Functions . . . . . . . . . . . . . . . . . . . .. 3-48
Nonmaskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .. 3-48

v
System Control Port B (Hex 0061) . . . . . . . . . . . . . . . . . . 3-48
System Control Port A (Hex 0092) . . . . . . . . . . . . . . . . . . 3-50
Power-On Password ........................... 3-52
Hardware Compatibility ........................... 3-53

Index ........................................ X-1

vi
Figures

1-1. Model and Submodel Bytes ................... 1-3
1-2. System Board Devices and Features ............. 1-4
1-3. System Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1-4. System Board I/O Address Map ................ 1-6
1-5. Performance Specifications-Type 1 ............. 1-7
....6. Performance Specifications-Type 2 ............. 1-8
1-7. Physical Specifications ...................... 1-9
2-1. POS I/O Address Map ....................... 2-5
2-2. Card Selected Feedback Register (Hex 0091) ....... 2-6
2-3. System Board Enable/Setup Register (Hex 0094) ..... 2-7
2-4. System Board POS Register 2 (Hex 0102) .......... 2-8
2-5. Parallel Port Select Bits ..................... 2-8
2-6. System Board POS Register 3, Type 1 (Hex 0103) 2-9
2-7. POS Register 3 (Bits 3,2) Type 1 ............... 2-10
2-8. POS Register 3 (Bits 1, 0) Type 1 ............... 2-10
2-9. POS Register 3, Type 2 ..................... 2-11
2-10. POS Register 3 (Bits 3, 2), Type 2 .............. 2-11
2-11. R1 and T1 Bit Values, Type 2 ................. 2-11
2-12. Adapter Enable/Setup Register (Hex 0096) ........ 2-12
3-1. Matched-Memory Extension Voltage and Signal
Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-2. Matched-Memory Cycle (No Waits) .............. 3-9
3-3. Matched-Memory Cycle with One Wait .. . . . . . . . .. 3-11
3-4. Arbitration Bus Priority Assignments ............ 3-13
3-5. Arbitration Register, Write to Hex 0090 .......... 3-14
3-6. Arbitration Register, Read Hex 0090 ............ 3-14
3-7. Memory Error Address Reassignment ........... 3-18
3-8. Memory Encoding Register (Type 1) ............ 3-20
3-9. Memory Encoding Register, Bits 7 and 6 (Type 1) 3-20
3-10. Memory Encoding Register, Bits 5 and 4 (Type 1) 3-21
3-11. Memory Encoding Register, Bits 3,2, and 1 (Type 1) . 3-22
3-12. Split Address Register (Type 1) ............... 3-22
3-13. Memory Encoding Register 1 (Type 2) ........... 3-23
3-14. Memory Encoding Register 1, Bits 5 and 4 (Type 2) .. 3-23
3-15. Memory Encoding Register 1, Bits 3-1 (Type 2) .... 3-25
3-16. Memory Encoding Register 2 (Type 2) ........... 3-25
3-17. Memory Encodi ng Register 2, Bits 5 and 4 (Type 2) .. 3-26
3-18. System Memory Map 1, (Type 1 and Type 2 ) ...... 3-27
3-19. System Memory Map 2, (Type 1 and Type 2) ....... 3-27

vII
3-20. System Memory Map 3, (Type 1) . . . . . . . . . . . . . . . 3-28
3-21. System Memory Map 3, (Type 2) . . . . . . . . . . . . . . . 3-28
3-22. System Memory Map 4, (Type 1) . . . . . . . . . . . . . . . 3-29
3-23. System Memory Map 4, (Type 2) . . . . . . . . . . . . . . . 3-29
3-24. System Memory Map 5, (Type 1) . . . . . . . . . . . . . . . 3-30
3-25. System Memory Map 5, (Type 2) . . . . . . . . . . . . . . . 3-30
3-26. System Memory Map 6, (Type 1) . . . . . . . . . . . . . . . 3-31
3-27. System Memory Map 6, (Type 2) . . . . . . . . . . . . . . . 3-31
3-28. System Memory Map 7, (Type 2 ) . . . . . . . . . . . . . . 3-32
3-29. System Memory Map 8, (Type 2) . . . . . . . . . . . . . . . 3-33
3-30. System Board Memory Connector Pin Locations .... 3-33
3-31. System Board Memory Connector .. . . . . . . . . . . .. 3-35
3-32. RT/CMOS RAM Address Map . . . . . . . . . . . . . . . . . 3-36
3-33. RT/CMOS Address Register and NMI Mask (Hex 0070) 3-37
3-34. RT/CMOS Data Register (Hex 0071) . . . . . . . . . . . . . 3-37
3-35. Real-Time Clock Bytes . . . . . . . . . . . . . . . . . . . . . 3-39
3-36. Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3-37. Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3-38. Status Register C . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3-39. Status Register D . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3-40. Diagnostic Status Byte . . . . . . . . . . . . . . . . . . . . . 3-43
3-41. Diskette Drive Type Byte . . . . . . . . . . . . . . . . . . . . 3-44
3-42. Diskette Drive Type Byte (Bits 7 - 4) . . . . . . . . . . . . 3~44
3-43. Diskette Drive Type Byte (Bits 3 - 0) . . . . . . . . . . . . 3-44
3-44. Equipment Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3-45. Equipment Byte (Bits 7,6) . . . . . . . . . . . . . . . . . . . 3-46
3-46. Equipment Byte (Bits 5, 4) . . . . . . . . . . . . . . . . . . . 3-46
3-47. System Control Port B (Write) . . . . . . . . . . . . . . . . . 3-49
3-48. System Control Port B (Read) . . . . . . . . . . . . . . . . . 3-49
3-49. System Control Port A . . . . . . . . . . . . . . . . . . . . . . 3-50

vIII
Section 1. System Overview

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
System Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
System Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1-5
System Board I/O Address Map . . . . . . . . . . . . . . . . . . . . . . 1-6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Model 80 System Overview 1-1
Notes:

1