Text preview for : Fujitsu-Siemens LifeBook N6210 - QUANTA AW3 - REV 1A.pdf part of FUJITSU-SIEMENS Fujitsu-Siemens LifeBook N6210 - QUANTA AW3 - REV 1A FUJITSU-SIEMENS Fujitsu-Siemens LifeBook N6210 - QUANTA AW3 - REV 1A.pdf
Back to : Fujitsu-Siemens LifeBook | Home
5 4 3 2 1
AW3 Block Diagram 1
Dothan+Alviso(915PM)+ICH6-M
D
Intel CPU Thermal Clock Gen. D
Dothan/Yonah Sensor ICS954201
27W/31W MAX6642ATT98-T
VRAM 478 PIN micro FC-BGA PG 4
64MB/128MB/ PG 3
PG 4,5
256MB
PG 19,20 FSB
400/533MHz
LCD Panel LVDS
PG 20
PCIE x 16
VGA Chip Channel A
2.5Gb/s MCH DDR-SODIMM1 PG 10
CRT Port R,G,B ATI M24 Memory Control Hub DDR2 INTERFACE, 400/533MHz
PG 21 Channel B
708 BGA
Alviso 915PM DDR-SODIMM2 PG 10
S-Video TV
C PG 21 PG 14~19 1257 Pin BGA C
PG 6~9
HDTV
PG 21 Spread Spectrum
PG 14
DMIx4
PATA 66/100 33MHZ, 3.3V PCI BUS
ODD PG 12 HDD-1 PG 12
ICH6-M LAN
PATA Marvell SATA I/O Control Hub CARDBUS MINI-PCI BCM4401
HDD-2 PG 29 88SA8040 TI7411
PG 29 BCM5788
PG 22,23 PG 26 PG 24
POWER Block Diagram
MAX1632
82801FBM RJ45
B
PG36 USB 2.0 609 BGA PG 25 B
12V 5VPCU 3VPCU
USB PORT 0,1,2,3 Express
USB Conn. PG 30
MAINON SUSON RVCCON SUSON MAINON
Card
USB PORT 4 PG 11,12,13
PG 22
VCC5 5VSUS RVCC3 3VSUS VCC1.5 IR Receiver PG 30
VIN VIN
Azalia 3.3V LPC
USB PORT 5 33MHz
VRON MAX1907 MAX1993 MAINON TV MODULE PG 30
PG32 PG33
VCC_CORE VGACORE USB PORT 6
MAINON RVCC_ON SUSON Finger Printer PG 30 EC/KBC
MDC Audio Codec PC87591
MAX1715 MAX1844
PG34 PG35
ALC260
VCC2.5 RVCC1.5 1.8VSUS
176 Pins LQFP PG 31
FAN
PG 26 PG 27 PG 27
A MAINON A
SUSON G2996 MAINON G2996 MAINON
VCC1.8
PG34 PG35
RJ11 Amp MIC Amp TouchPAD Keyboard Flash BOM
VMEM_VTT VCC1.5 SMDDR_VTERM
PG 25 PG 27 PG 27 PG 28 PG 30 PG 30 PG 31
QUANTA
VRON SC338 MAINON
VIN
PG33 Title
COMPUTER
GMCH_VTT VCC1.2 System Block Diagram
LP2951 HP Int SPK Size Document Number R ev
PG38
PG 27 PG 28 Custom
AW3 1A
REF3V
Date: Tuesday, March 15, 2005 Sheet 1 of 41
5 4 3 2 1
1 2 3 4 5 6 7 8
Voltage Rails
VCC_CORE
Voltage Rails
Core voltage for Processor
ON S0~S2
X
ON S3 ON S4/S5 G3 Ctl Signal
VR_ON
Board Stack up Description
PCB Layers VID
Power On Sequencing Timing Diagram
2
Layer 1 TOP(FSB,DDR2,CLK,PCIE Component)
GMCH_VTT Core voltage for CPU / NB X VR_ON VR_ON Tsft_star_vcc
SMDDR_VREF 0.9V for DDR2 Termination voltage X MAINON Ground Plane Vboot
Layer 2 Vcc-core Tboot
VMEM_VTT 1.25V for VRAM Termination voltage X MAINON Tboot-vid-tr
A
Layer 3 IN1(FSB,CLOCK,DDR2,PEG,CLK) A
VGA_CORE VGA CORE (powerplay 1.0V to 1.2V) X MAINON CPU_UP Tcpu_up
Layer 4 IN2(PCI,IDE,LPC)
RVCC1.5 X X X RVCC_ON
Layer 5 Power Plane
RVCC3 X X X RVCCD Vccp_UP Tvccp_up
Layer 6 BOTTOM, (Component,Other)
Vccgmch
VCC1.2 X VGA_P_REF
VCC1.5 X MAINON GMCHPWRGD Tgmch_pwrgd
VCC1.8 X MAINON
CLK_ENABLE#
VCC2.5 X MAINON
VCC3 X MAIND IMVP4_PWRGD Tcpu_pwrgd
VCC5 X MAIND
1.8VSUS X X SUSON
3VSUS X X SUSD
B 5VSUS X X SUSD B
3VPCU X X X X VL
5VPCU X X X X VL
9VPCU X X X X 5VPCU
ACIN POWER ON TIMING Power Sequencing and Reset Signal Timings CPU Power On Sequence
Hub interface "CPU
ACIN Reset Complete"
message
5VPCU/3VPCU VR_ON Tsft_star_vcc
STPCLK#,CPUSLP#,
NBSWON# STP_CPU#,STP_PCI# Vboot
SLP_S1#,C3_STAT# Tboot
Vcc-core Tboot-vid-tr
PWRBTN# Frequency Strap Values Normal
To ICH6 Straps Operation] Tcpu_up
CPU_UP
2~3RTC
PCIRST#
RCVV_ON
Vccp
32~38RTC
To ICH6 SUS_STAT# Tvccp_up
C
RSMRST#
Vccp_UP C
PWROK, 99ms
VGATE
SUSB#,SUSC#
Vccgmch
Vcc3_3, Vcc1_5, 0ms
From ICH6 VCCHI, V_CPU_IO Tgmch_pwrgd
SUSON
GMCHPWRGD
0ms
From 87591 CLK_ENABLE#
MAINON
10ms
From 87591 LAN_PWROK Tcpu_pwrgd
VSUS,VCC
IMVP4_PWRGD
VccLAN3_3, 0ms
From 87591 VccLAN1_5
VR_ON
1~2RTC
SLP_S3#
GMCH_VTT/1.05V
1~2RTC
SLP_S4#
VCORE_CPU
V5Ref 110ms
CK410_PWRGD SLP_S5#
To clock generator
110ms
SUSCLK
99ms < t 214 10ms
D PWROK/IMVP_PWRGD D
To GMCH/other RSMRST#
PLTRST#\PCIRST# PCI device
VccSus3_3, 0ms
H_PWRGD From ICH6 to CPU
VccSus1_5
QUANTA
0ms
V5RefSus
Title
COMPUTER
2ms 5ms
H_CPURST# Form GMCH to CPU RTCRST# System Block Diagram
Size Document Number R ev
Custom 1A
VccRTC AW3
Date: Tuesday, March 15, 2005 Sheet 2 of 41
1 2 3 4 5 6 7 8
A B C D E
FSC FSB FSA CPU SRC PCI
1
0
0
0
0
0
1
1
1
1
1
0
100
133
166
200
100
100
100
100
33
33 Default
33
33
Place these termination
3
4,10,11,12,13,14,15,16,17,20,21,22,23,24,25,26,27,29,30,31,32,33,36 VCC3
4,5,6,7,8,9,11,13,33 GMCH_VTT to close CK410M.
0 0 0 266 100 33
1 0 0 333 100 33 CLK_VDDA R98 49.9/F
4 4
1 1 0 400 100 33 C165 R99 49.9/F
CG_XIN
1 1 1 RESERVED R100 49.9/F
2
33P R101 49.9/F ICS FAE Recommend.
37
38
Y1 U18
14.318MHZ 50 52 14M_REF R117 22/F
VDDA
GNDA
CL=20p XTAL_IN REF0 14M_ICH 12
C166 RP9
1
CG_XOUT 49 44 RHCLK_CPU 1 2 C223
XTAL_OUT CPU0 HCLK_CPU 4
43 RHCLK_CPU# 3 4
CPU0# HCLK_CPU# 4
33P RP10 33X2 *10P
CLK_EN# 10 41 RHCLK_MCH 1 2
32 CLK_EN# Vtt_PwrGd#/PD CPU1 HCLK_MCH 6
55 40 RHCLK_MCH# 3 4
12 STP_PCI# PCI/SRC_STOP# CPU1# HCLK_MCH# 6
54 33X2
12,32 STP_CPU# CPU_STOP#
CPU2_ITP/SRC7 36
CPU2#_ITP/SRC7# 35
EC1 SMbus address D2
CGCLK_SMB 46 CK-410M 33
R176 12.1/F CGDAT_SMB SCLK SRC6
22 CLK48_7411 47 SDATA SRC6# 32
RP11
R177 12.1/F CG_BSEL0 12 31 RSRC_MCH 1 2 SRC_MCH R103 49.9/F
12 CLK48_USB FSA/USB_48MHz SRC5 SRC_MCH 7
CG_BSEL1 16 30 RSRC_MCH# 3 4 SRC_MCH# R104 49.9/F
FSB/TEST_MODE SRC5# SRC_MCH# 7
CG_BSEL2 R124 4.7K R_CG_BSEL2 53 RP26 33X2
FSC/REF1 RSRC_ICH SRC_ICH R167 49.9/F
SRC4_SATA 26 3 4 SRC_ICH 12
CLK_VDDREF 48 27 RSRC_ICH# 1 2 SRC_ICH# R168 49.9/F
VDD_REF SRC4#_SATA SRC_ICH# 12
CLKVDD 42 RP25 33X2
VDD_CPU RSRC_SATA SRC_SATA R165 49.9/F
SRC3 24 3 4 SRC_SATA 11
CLKVDD1 1 25 RSRC_SATA# 1 2 SRC_SATA# R166 49.9/F
VDD_PCI_1 SRC3# SRC_SATA# 11
7 33X2
VDD_PCI_2 SRC_NEW R163 49.9/F
3 SRC2 22 3
CLKVDD 21 23 SRC_NEW# R164 49.9/F
VDD_SRC0 SRC2# RP24
ICS FAE Recommend. 28 VDD_SRC1
R140 4.7K for isolation pin53 REF1 CLK output. 34 19 RSRC_NEW 3 4 SRC_PEG R161 49.9/F
VDD_SRC2 SRC1 SRC_NEW 22
20 RSRC_NEW# 1 2 SRC_PEG# R162 49.9/F
SRC1# SRC_NEW# 22
CLK_VDD48 11 RP23 33X2
VDD_48 RSRC_PEG
SRC0/DREFSSCLK 17 3 4 SRC_PEG 14
Iref=5mA, R102 475/F IR EF 39 18 RSRC_PEG# 1 2
Ioh=4*Iref IREF SRC0#/DREFSSCLK# SRC_PEG# 14
33X2
5 R_PCLK_591 R145 33
PCI5 PCLK_591 31
4 R_PCLK_7411 R169 33
PCI4 PCLK_7411 22
3 R_PCLK_LAN R144 33
GND_PCI_1
GND_PCI_2
PCI3 PCLK_LAN 24
GND_SRC
GND_CPU
R_PCLK_MINI
GND_REF
14 56 R122 33
DOT96MHz PCI2 PCLK_MINI 26
GND_48
15 9 R_PCLK_ICH R175 33
DOT96MHz# PCIF1/100_96M# PCLK_ICH 11
8 R_PCLK_SIO R170 10K
PCIF0/ITP_EN VCC3
ICS954201 250mA ( MAX. )
Place these termination
13
51
2
6
29
45
R171 10K
to close CK410M.
VCC3
R146 *10K
L34
VCC3 1 2 CLKVDD
ACB2012L-120 DREFSSCLK Frequency Select.
12 0 ohms@100Mhz C193 C195 C303 C329 C286 GMCH_VTT "0" : 96MHz VCC3
"1" : 100MHz
2
0.047U 0.047U 0.047U 0.047U 4.7U 2
R138 R135 R112 R108
R126 2.2
2
1 2 CLK_VDDA *1K *1K 10K 10K
C194 C238 R151 0 CG_BSEL1 R142 1K 3 1 CGDAT_SMB
4 SELPSB1_CLK MCH_BSEL1 6 10,12 PDAT_SMB
0.047U 4.7U R132 0 CG_BSEL2 R127 1K Q23 RHU002N06
4 SELPSB0_CLK MCH_BSEL2 6
R157 R129 VCC3
L37
VCC3 1 2 CLKVDD1 *0 *0