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5 4 3 2 1
Power
VCORE
Page 80
F83Vf MonteVina BLOCK DIAGRAM System
Page 81
D D
1.5VS & 1.05VS
Page 82
DDR & VTT
CPU Page 83
MEROM / PENRYN
1.8VS
Page 3~5 Page 84
FSB 1066MHz VGA_VCORE
Page 85
LVDS Page 45
NVIDIA Charger
PCIE x16 DDR3 1066MHz Dual Channel DDR3 Page 88
CRT Page 46
N10P-GV2 PM-45 SO-DIMM X 2 Detect
HDMI Page 90
Page 48
Page 7 ~ 9
C Page 70~79 Page 10~15 Load Switch C
Page 91
x4 DMI
Power Protect
10/100 LAN Page 92
PCI-E LAN PCI-E LPC Power Protect
AR8132 33MHz Debug Conn.
Page 93
Page 44
Page 33 ~ 34
ICH9-M EC ITE8512 SPI ROM
Page 30
Page 30 ~ 31
Page 20 ~ 24
SATA
NEWCARD
Page 53
SATA HDD
B B
Page 51
Azalia AUDIO AMP
SATA ODD RLT ALC269 Page 37
Page 36
AUDIO JACK &
Page 51 MIC Page 38
USB
USB 2.0
USB CCD
X4
FAN + SENSOR Page 52 Page 45
Page 50
BLUE TOOTH
Power On Sequence Module
Page 02 Page 61
PWR / EXGATE Switch
A
Page 55 Card Reader 4 in 1 Card A
Alcor AU6433 Reader
PWR Discharge Page 40 Page 40
Page 57
Finger Printer
(NO STUFF) Title : Block Diagram
PEGATRON COMPUTER INC Engineer: Zack Kuo
Page 63
Size Project Name
F83Vf Rev
C 1.1
P/N
Date: Thursday, July 16, 2009 Sheet 1 of 100
5 4 3 2 1
5 4 3 2 1
Reset
IC
D D
PWRSW#_EC 6 Power On
2 SWITCH
+5VA
AC_BAT_SYS 1 7 PM_PWRBTN#
+3VA_EC SLP_S4#
+3VA EC
To EC
+3VA_EC 5 PM_RSMRST# ICH9
IT8511E SLP_S3#
3 VSUS_ON
VRMPWRGD
EC_CLK_EN
CL_PWROK
13 PWROK
+3VSUS 4 VSUS_GD#
+5VSUS
SUSB_ON
SUSC_ON
+12VSUS
PLT_RST#
H_PWRGD
8 16
ALL_SYSTEM_PWRGD
16
SUSC_ON
C
+1.5V C
+3V
+5V
+12V 17
CPU_PWRGD
H_CPURST#
10 15 PM45 PENRYN
CL_PWROK
ICH8_PWROK
PWROK
12
+VGA_VCORE
+1.8VS 14
+1.25VS
CLK_PWRGD
+2.5VS CLK
9 +3VS Gen.
+5VS CLK_PWRGD asserted when both
SUSB_ON
+12VS PM_SUSB# and VRM_PWRGD are
high.
B B
Delay 11 CPU_VRON Power On Sequence
99ms
+VCORE
1 17
A A
Title : Power Sequence
PEGATRON COMPUTER INC Engineer: Zack Kuo
Size Project Name
F83Vf Rev
C 1.1
P/N
Date: Thursday, July 16, 2009 Sheet 2 of 100
5 4 3 2 1
5 4 3 2 1
H_D#[63:0]
<10> H_D#[63:0]
H_A#[35:3]
<10> H_A#[35:3]
H_REQ#[4:0]
<10> H_REQ#[4:0]
D D
T0318
T0319
1
U0301A U0301B
1
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# <10> D[0]# D[32]#
ADDR GROUP 0
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# <10> D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# <10> D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
A[6]# D[3]# D[35]#
DATA GRP 0
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A[7]# DEFER# H_DEFER# <10> D[4]# D[36]#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# <10> D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# <10> D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
H_A#11 A[10]# +VCCP_CPU H_D#8 D[7]# D[39]# H_D#40
P5 F1 K24 Y25
A[11]# BR0# H_BR0# <10> QC D[8]# D[40]#
DATA GRP 2
H_A#12 P2 H_D#9 G24 W22 H_D#41
A[12]# D[9]# D[41]#
CONTROL
H_A#13 L2 D20 H_IERR# R0309 1 2 49.9Ohm H_D#10 J24 Y23 H_D#42
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43
P4 A[14]# INIT# B3 H_INIT# <20> J23 D[11]# D[43]# W24
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# <10> F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
<10> H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
C1 H_D#15 H23 AB25 H_D#47
RESET# H_CPURST# <10> D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 <10> <10> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <10>
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 <10> <10> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <10>
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 <10> <10> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <10>
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# <10>
H_REQ#4 L1 REQ[4]# H_D#16 H_D#48
HIT# G6 H_HIT# <10> N22 D[16]# D[48]# AE24
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# <10> D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# XDP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1 H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
QC
DATA GRP 1
H_A#21 U4 AD1 XDP_BPM#2 H_D#21 M24 AC26 H_D#53 Comp 0,2: Zo=25 Ohm, trace length < 0.5"
H_A#22 A[21]# XDP/ITP SIGNALS BPM[2]# XDP_BPM#3 H_D#22 D[21]# D[53]# H_D#54
Y5 AC4 L22 AD20
H_A#23 U1
A[22]# BPM[3]#
AC2 H_PRDY# H_D#23 M23
D[22]# D[54]#
AE22 H_D#55 Comp 1,3: Z0=50 Ohm, trace length < 0.5"
H_A#24 A[23]# PRDY# H_PREQ# H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 H_TCK H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK H_TDI H_D#26 D[25]# D[57]# H_D#58
C T3 AA6 P22 AE21 C
DATA GRP 3
A[26]# TDI D[26]# D[58]#
H_A#27
H_A#28
H_A#29
W2
W5
Y4
A[27]#
A[28]#
A[29]#
TDO
TMS
TRST#
AB3
AB5
AB6
H_TDO
H_TMS
H_TRST#
+VCCP_CPU H_D#27
H_D#28
H_D#29
T24
R24
L25
D[27]#
D[28]#
D[29]#
D[59]#
D[60]#
D[61]#
AD21
AC22
AD23
H_D#59
H_D#60
H_D#61
DC Comp 0,2: Zo=27.4 Ohm, trace length < 0.5"
Comp 1,3: Z0=55 Ohm, trace length < 0.5"
2
H_A#30 U2 C20 H_DBR# H_D#30 T25 AF22 H_D#62
H_A#31 A[30]# DBR# R0315 H_D#31 D[30]# D[62]# H_D#63
V4 A[31]# N25 D[31]# D[63]# AC23
H_A#32 W3 1KOhm L26 AE25
A[32]# <10> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <10>
H_A#33 AA4 THERMAL 1% M26 AF24
A[33]# <10> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <10>
H_A#34 AB2 N24 AC20
<10> H_DINV#1 H_DINV#3 <10>
1
H_A#35 A[34]# DINV[1]# DINV[3]#
AA3 A[35]# PROCHOT# D21 H_PROCHOT_S#
V1 A24 GTL_REF AD26 R26 H_COMP0 R0311 1 2 24.9Ohm 1%
<10> H_ADSTB#1 ADSTB[1]# THRMDA CPU_THRM_DA <50> GTLREF COMP[0]
T0320 1 B25 R0317 2 @ 1% 1 1KOhm C23 MISC U26 H_COMP1 R0312 1 2 49.9Ohm 1%
THRMDC CPU_THRM_DC <50> TEST1 COMP[1]
2
A6 R0318 2 @ 1% 1 1KOhm D25 AA1 H_COMP2 R0313 1 2 24.9Ohm 1%
<20> H_A20M# A20M# TEST2 COMP[2]
1
ICH
A5 C7 R0316 T0304 1 C24 Y1 H_COMP3 R0314 1 2 49.9Ohm 1%
<20> H_FERR# FERR# THERMTRIP# H_THRMTRIP# <5,11,20,32> TEST3 COMP[3]
C4 C0301 2KOhm T0305 1 AF26
<20> H_IGNNE# IGNNE# TEST4
T0321 1 1 T0302 0.1UF/10V 1% T0306 1 AF1 E5 H_DPRSTP# <11,20,80>
2
@ T0307 TEST5 DPRSTP#
<20> H_STPCLK# D5 CLK_CPU_BCLK <29> 1 A26 B5 H_DPSLP# <20>
1
STPCLK# TEST6 DPSLP#
2
<20> H_INTR C6 LINT0 H CLK DPWR# D24 H_DPWR# <10>
B4 A22 R0339 B22 D6
<20> H_NMI LINT1 BCLK[0] <29> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD <20>
A3 A21 100Ohm