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5 4 3 2 1
PROJECT U5A
Revision History
S R 2 0 0 5 / 0 5 / 1 7
D R1.0 D
E R 2 0 0 5 / 0 8 / 0 4
R1.1
P R 2 0 0 5 / 1 0 / 0 7
R2.0
S M B S i g n a l s
Power States
Host Name Devices Address
Chipset SMBCK,SMBDA
SIGNAL SLP_S3# SLP_S4# SLP_S5# +*VALWAYS +*V +*VS Clocks
ICH6-M 10h STATE
ADT7473(Thermal) 2Eh
ICS954213(Clock Genertor) Full ON HIGH HIGH HIGH ON ON ON ON
D2h
DDR2 SO-DIMM A0h
S3(Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4(Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
C C
S5/Sort OFF LOW LOW LOW ON OFF OFF OFF
P C I D e v i c e s
APIC
Bus# Device# Function# REQ/GNT# IDSEL Interrupts Device Function
Bus0 Device00 Function0 Intel 915GM Host Bridge / DRAM Controller
Bus0 Device01 Function0 Intel 915GM Virtual PCI to PCI
Bus0 Device02 Function0 Intel 915GM GMCH Integrated Graphics Device
Bus0 Device27 Function0 Azalia Controller
Bus0 Device28 Function0 PCI Express Port1
Bus0 Device28 Function1 PCI Express Port2
B B
Bus0 Device28 Function2 PCI Express Port3
Bus0 Device28 Function3 PCI Express Port4
Bus0 Device29 Function0 A# Intel UHCI USB Controller
Bus0 Device29 Function1 D# Intel UHCI USB Controller
Bus0 Device29 Function2 C# Intel UHCI USB Controller
Bus0 Device29 Function3 A# Intel UHCI USB Controller
Bus0 Device29 Function7 H# Intel EHCI USB Controller
Bus0 Device30 Function0 PCI to PCI Bridge
Bus0 Device30 Function2 B# Intel Audio Controller
Bus0 Device30 Function3 B# Intel Modem Controller
Bus0 Device31 Function0 Intel PCI-to-LPC Bridge
Bus0 Device31 Function1 C# Intel IDE Controller
Bus0 Device31 Function2 SATA Controller
Bus1 Device03 Function0 2 AD19 F# CardBus Bridge
A Bus1 Device03 Function1 2 AD19 G# IEEE 1394 A
Bus1 Device03 Function2 2 AD19 E# SD Card Interface
Bus1 Device03 Function3 2 AD19 E# Memory Stick Interface
Bus1 Device03 Function4 2 AD19 E# xD Picture Card Interface Project Name
U5A
Bus1 Device04 Function0 1 AD20 E# Ethernet Controller
ASUSTek COMPUTER INC Engineer: HF_Lin
Bus1 Device05 Function0 3 AD21 C#/D# Mini PCI
Size Rev
Custom Title : Table of Contens 2.0
Date: Tuesday, September 27, 2005 Sheet 1 of 46
5 4 3 2 1
A B C D E
DOTHAN/ALVISO-GM BLOCK DIAGRAM
Fan & Thermal
1 CLOCK GEN.
ICS954213 22
DOTHAN Sensor 26
1
478 uFCPGA ADT7473
533MHz 4,5
FSB 4.2GBytes/Sec
LCD_CN &
Invertor27 Dual Channel DDR2 8.5GBytes/Sec
ALVISO
GMCH
CRT 1257 uFCBGA ON BOARD
2
Port 29
DDR2 SO-DIMM 2
6,7,8,9,10
512MB DDR2 ONE Slot 13
11,12
RTC Conn.
32 Direct Media Interface
2GBytes/Sec(Lane*4)
PID, PCB ID
32
SM_BUS
31 POWER UP,
ICH6-M RESET 23
USB2.0
2*USB2.0 30 609 uFCBGA
PCI_BUS 3.3V, 33MHz
PCI Express
Bluetooth_CN USB2.0 15,16,17 AC LINK
3 3
30
IDE_BUS LAN MINI PCI
RealTek 8111B TYPE II
18 20
LPC, 33MHz ADI 1986A
24
POWER CDROM_CN
28
HDD_CN28
LAN I/O
VCORE 19
40 AUDIO AMP
Keyboard 25
CHARGE 42 Controller FWH TPM
M38857HP 21 26 34
4 4
SYSTEM 36
MIC.
BATLOW/SD# PREAMP 25
40
Internal
BAT_CONNECT Keyboard
&TP 32
41
1.8V
37
1.5VS & 1.05VS
5 38
TOUCH PAD AUDIO BOARD IO SUB BD INSTANT BD 5
PWR HALL
LOAD Switch35 TP SW MDC R5C841 DC JACK BUT. LEDs Sensor Project Name
TP CONN. LED HP JACK MIC JACK LEDs U5A
ASUSTek COMPUTER INC Engineer: HF_Lin
Size Rev
Custom Title : BLOCK DIAGRAM 2.0
Date: Tuesday, September 27, 2005 Sheet 2 of 46
A B C D E
A B C D E
M38857MB_GPIO Use As Signal Name Describtion ICH6_GPIO Use As Signal Name
P20 GPO ANKEY_RSM Anykey wakeup GPI7 GPI MEMORY_FREQ
1 1
P21 GPI8 GPI EXTSMI#
P22 GPO BAT_LEARN Switch AC power on or off GPI11 GPI LID_RSM#
P23 GPO 802_ON# Notify wireless LED status change GPI12 GPI KB_SCI#
P27 GPO SCROLLOCK#_3 GPI13 GPI
P42 GPO GPO18 GPO STP_PCI#
P43 GPI LID_RSM# Notify LID switch status GPO19 GPO PWRLED_1HZ
P44 GPO KBDCPURST_3Q GPO21
P45 GPO A20GATE_3Q GPO23 GPO FWH_WP#
2 2
P46 GPO KBDSCI_3Q Trigger EC's SCI event GPIO25 GPO CB_SD#
P47 GPIO CLKRUN#_3 GPIO27 GPI PCB_ID0
P50 GPI BAT_LLOW#_OC Battery low event GPIO28 GPI PCB_ID1
P51 GPI40 GPI PANEL__ID0
P52 GPO GPI41 GPI PANEL__ID1
P53 GPO BTPWRCL# Control Bule Tooth on/off
P54 GPI BAT_TYPE_3S1P# Show battery type
3 P55 GPI BAT_IN#_OC Battery IN/OUT event 3
P56 GPO CODEC_SHDN# Switch CODEC power on/off
P57 GPO TPD_LED_OFF# Switch TPD LED on/off
P67 GPO WIRELESS_LAN_ON# Control wireless LAN module on/off
P66 GPI BAT_SAVING#
P65
P64 GPI ACIN_OC AC IN / OUT event
P63 GPO
4 4
P62 GPI CHG_FULL_OC End of charger status
P61
P60
P77 GPO SMC_BAT
P76 GPIO SMD_BAT
P26 GPI KBNUM#_3 Notify NUM key status change
P25 GPI KBCAP#_3 Notify CAP key status change
P24 GPO PCIRST#_GATE Block PCIRST# during S3 resume
5 5
P40 Project Name
U5A
ASUSTek COMPUTER INC Engineer: HF_Lin
Size Rev
Custom Title : SYSTEM INFORMATION 2.0
Date: Tuesday, September 27, 2005 Sheet 3 of 46
A B C D E
5 4 3 2 1
+VCCP
H_D#[0:63] 6
T126 T127
TPC26T TPC26T
1
R1 U1A
1
1
H_D#15 C25 Y25 H_D#47
6 H_A#[3:16] D[15]# D[47]#
U1B 56Ohm H_D#14 E23 AA26 H_D#46
H_A#16 H_D#13 D[14]# D[46]# H_D#45
AA2 A[16]# ADS# N2 H_ADS# 6 B23 D[13]# D[45]# Y23
H_A#15 T128 T129 H_D#12 H_D#44
2
Y3 A[15]# PRDY# A10 1 C26 D[12]# D[44]# V26
H_A#14 AA3 B10 TPC26T 1 TPC26T H_D#11 E24 U25 H_D#43
H_A#13 A[14]# PREQ# H_D#10 D[11]# D[43]# H_D#42
U1 A[13]# D24 D[10]# D[42]# V24
DATA GROUP 0
H_A#12 H_D#9 H_D#41
2
D Y1 A[12]# BNR# L1 H_BNR# 6 B24 D[9]# D[41]# U26 D
H_A#11 Y4 J3 H_D#8 C20 AA23 H_D#40
H_BPRI# 6
DATA GROUP
A[11]# BPRI# D[8]# D[40]#
ADDRESS GROUP 0
H_A#10 W2 H_D#7 B20 R23 H_D#39
H_A#9 A[10]# T130 H_D#6 D[7]# D[39]# H_D#38
T4 A[9]# A21 D[6]# D[38]# R26
H_A#8 W1 A7 1 H_D#5 B26 R24 H_D#37
H_A#7 A[8]# DBR# H_D#4 D[5]# D[37]# H_D#36
V2 A[7]# TPC26T A24 D[4]# D[36]# V23
H_A#6 R3 H_D#3 B21 U23 H_D#35
H_A#5 A[6]# H_D#2 D[3]# D[35]# H_D#34
V3 A[5]# A22 D[2]# D[34]# T25
H_A#4 U4 L4 H_D#1 A25 AA24 H_D#33
A[4]# DEFER# H_DEFER# 6 D[1]# D[33]#
H_A#3 P4 H2 H_D#0 A19 Y26 H_D#32
A[3]# DRDY# H_DRDY# 6 D[0]# D[32]#
6 H_ADSTB#0 U3 ADSTB[0]# DBSY# M2 H_DBSY# 6 6 H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 6
H_REQ#4 T1 C23 W25
REQ[4]# 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#3 P1 C22 W24
REQ[3]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
H_REQ#2 T2
H_REQ#1 REQ[2]# +VCCP H_D#31 H_D#63
P3 REQ[1]# K25 D[31]# D[63]# AF26
H_REQ#0 R2 H_D#30 N25 AF22 H_D#62
REQ[0]# H_D#29 D[30]# D[62]# H_D#61
N4 H_BREQ#0 6 H26 AF25
CONTROL
BR0# H_D#28 D[29]# D[61]# H_D#60
6 H_REQ#[0:4] M25 D[28]# D[60]# AD21
H_D#27 N24 AE21 H_D#59
H_IERR# R2 D[27]# D[59]#
6 H_A#[17:31] IERR# A4 1 2 56Ohm H_D#26 L26 D[26]# D[58]# AF20 H_D#58
3
DATA GROUP 1
H_D#25 J25 AD24 H_D#57
H_A#31 H_D#24 D[25]# D[57]# H_D#56
DATA GROUP
AF1 A[31]# M23 D[24]# D[56]# AF23
H_A#30 AE1 B5 H_D#23 J23 AE22 H_D#55
A[30]# INIT# H_INIT# 15 D[23]# D[55]#
H_A#29 AF3 H_D#22 G24 AD23 H_D#54
H_A#28 A[29]# H_D#21 D[22]# D[54]# H_D#53
AD6 A[28]# F25 D[21]# D[53]# AC25
ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#20 H24 AC22 H_D#52
A[27]# LOCK# H_LOCK# 6 D[20]# D[52]#
H_A#26 AD5 H_D#19 M26 AC20 H_D#51
H_A#25 A[26]# T131 H_D#18 D[19]# D[51]# H_D#50
AC6 A[25]# L23 D[18]# D[50]# AB24
H_A#24 AB4 TPC26T H_D#17 G25 AC23 H_D#49
C H_A#23 A[24]# H_D#16 D[17]# D[49]# H_D#48 C
AD2 A[23]# H23 D[16]# D[48]# AB25
H_A#22
1
AE4 A[22]# 6 H_DINV#1 J26 DINV[1]# DINV[3]# AD20 H_DINV#3 6
H_A#21 AD3 B11 K24 AE24
A[21]# RESET# H_CPURST# 6 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
H_A#20 AC3 L2 H_RS#2 L24 AE25
A[20]# RS[2]# 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
H_A#19 AC7 K1 H_RS#1
H_A#18 A[19]# RS[1]# H_RS#0 SOCKET479P
AC4 A[18]# RS[0]# H1
H_A#17 AF4 A[17]# H_RS#[0:2] 6
6 H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# 6
HIT# K3 H_HIT# 6
6 H_DPWR# C19 DPWR# HITM# K4 H_HITM# 6
SOCKET479P
Resistor placed within +VCCP +VCCP
U1C
0.5''of processor pin.
22 CLK_CPU_BCLK B15 BCLK[0]
1
1
B14
HOSTCLK
22 CLK_CPU_BCLK# BCLK[1]
R3 1 2 49.9Ohm A16 AB1 H_COMP3 R4 1 2 54.9Ohm R5 R6
R9 ITP_CLK[0] COMP[3]
1 2 49.9Ohm A15 ITP_CLK[1] COMP[2] AB2 H_COMP2 R10 1 2 27.4Ohm
GND
P26 H_COMP1 R11 1 2 54.9Ohm 330Ohm 56Ohm
COMP[1] H_COMP0 R12 27.4Ohm
15 H_A20M# C2 A20M# COMP[0] P25 1 2
2
2
15 H_FERR# D3 FERR#
LEGACY CPU
A3 GND H_PWRGD
15 H_IGNNE# IGNNE#
B7 C9 H_PROCHOT#
15 H_DPSLP# DPSLP# BPM[3]#
6,15 H_CPUSLP# A6 SLP# BPM[2]# A9
D1 B8 +VCCP Resistor placed within
15 H_INTR LINT0 BPM[1]#
15 NMI_ICH D4 LINT1 BPM[0]# C8 0.5''of processor pin.
B B
15 H_SMI# B4 SMI#
1
15 H_STPCLK# C6 STPCLK# R14
H_PWRGD E4 AC1 R889 0Ohm
15 H_PWRGD PWRGOOD GTLREF[3]
G1 1 2 1KOhm
GTLREF[2] H_DPRSTP# 15
H_VID5 H4 E26
H_VID4 VID[5] GTLREF[1] GT_REF0
2
G4 VID[4] GTLREF[0] AD26
H_VID3 G3 H_VID5 RN1A 1 2
VID[3] 0OHM VR_VID5 40
1
H_VID2 F3 T132 H_VID4 RN1B 3 4
VID[2] 0OHM VR_VID4 40
H_VID1 F2 TPC26T R15 H_VID3 RN1C 5 6
VID[1] 0OHM VR_VID3 40
H_VID0 E2 C5 1 T133 H_VID2 RN1D 7 8
VID[0] TEST1 0OHM VR_VID2 40
F23 1 TPC26T 2KOhm
TEST2
MISC
T134 +VCCP H_VID1 R18 1 2 0Ohm
+V1.8S_PROC_VCCA3 VR_VID1 40
T135 TPC26T
2
1 AC26 VCCA[3]
GND
TPC26T 1 +V1.8S_PROC_VCCA2 N1 H_VID0 R19 1 2 0Ohm
GND
+V1.8S_PROC_VCCA1 VCCA[2]