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5 4 3 2 1
KAI Block Diagram SYSTEM DC/DC
TPS51120
Project code : 91.4F601.001 INPUTS OUTPUTS
PCB P/N : 05233 5V_S5
Intel CPU DCBATOUT
D
CLK GEN Revision : 1 3V_S5
D
ICS954305 Yonah/Merom
4,5 SYSTEM DC/DC
3
MAX8743
RGB CRT CRT 13
INPUTS OUTPUTS
Host BUS
533/667MHz 1D05V_S0
LVDS LCD DCBATOUT 1D8V_S3
14
DDRII DDRII 667 Channel A
Slot 0 nVIDIA
533/667 11
Calistoga SVIDEO TVOUT 13 MAXIM CHARGER
DDRII PM G72M-Z G3-64
Slot 1 DDR II 667 Channel B PCIE x 16 38,39,40 MAX8725
533/667 11 6,7,8,9,10
INPUTS OUTPUTS
C
BT+ C
1394 1394 DMI I/F
C
23
18V 3.0A
Ricoh 100MHz DCBATOUT
CAMERA30 5V 100mA
R5C832 PCI
SD/SDIO/MMC
CardReader
MS/MS Pro/xD
23 22,23 BLUE
TOOTH 30 CPU DC/DC
MAX8736ETL
M
USB 2.0 USB x 3 21
INPUTS OUTPUTS
RJ45 10/100 NIC
ICH7-M VCC_CORE
LCI
CONN 26 Intel 82562 25 SATA HDD 20
DCBATOUT
0.844~1.3V
44A
PATA ODD 20
PCB LAYER
B
RJ11
CONN
INTERNAL
MODEM
AMOM
N
HD Audio
15,16,17,18
LPC Bus L1:
L2:
Signal 1
GND
B
ARRAY MIC WAKIKI L3: Signal 2
MIC IN
PCIE x 1
USB 2.0 x 1
PCIE x 1
AUDIO CODEC PCIE+USB 2.0
L4: Signal 3
KBC
27
LINE OUT ENE KB3910SF L5: VCC
Ricoh 29
R5538 L6: Signal 4
SPDIF 26
L7: GND
Flash ROM
1MB 31 L8: Signal 5
OP AMP Thermal
Mini-Card Mini-Card Capacity Touch Int.
APA2031 28 New Card CIR & Fan
A
26 802.11a/b/g24 24 Button Pad 30 KB30 30 A
G792 19
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH DOCK Title
SPEAKER 10/100
CRT MIC IN LINE OUT S/PDIF TVOUT Ethernet CIR Block Diagram
15 Size Document Number Rev
A3
KAI 1
Date: Wednesday, April 19, 2006 Sheet 1 of 44
5 4 3 2 1
A B C D E
Calistoga Strapping Signals and ICS954305 Spread Spectrum Select ICH7M Integrated Pull-up
Configuration page 7 page 3 and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Pin Name Strap Description Configuration SS3 SS2 SS1 SS0 Spread Amount%
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
CFG[2:0] FSB Frequency Select 001 = FSB533 0 0 0 0 -0.5
011 = FSB667 EE_DOUT, GNT[5]#/GPO[17],
others = Reserved 0 0 0 1 -1.0 ICH6 internal 20K pull-ups
GNT[6]#/GPO[16], LDRQ[1]/GPI[41],
4 CFG[4:3] Reserved 0 0 1 0 -1.5
LAD[3:0]#/FB[3:0]#, LDRQ[0],
4
0 = DMI x2 0 0 1 1 -2.0
CFG5 DMI x2 Select 1 = DMI x4 (Default) PME#, PWRBTN#, TP[3]
0 1 0 0 -0.75
CFG6 0=Moby Dick
1=Calistoga 0 1 0 1 -1.25 LAN_RXD[2:0] ICH6 internal 10K pull-ups
0 = Reserved 0 1 1 0 -1.75
CFG7 CPU Strap 1 =Mobile CPU(Default) ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
0 1 1 1 -2.25
CFG8 Reserved ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
1 0 0 0 +/-0.25
0 = Reverse Lanes,15->0,14->1 ect.. SPKR, EE_CS,
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane 1 0 0 1 +/-0.5
Lane Reversal Numbered in order
1 0 1 0 +/-0.75 USB[7:0][P,N] ICH6 internal 15K pull-downs
CFG[11:10] Reserved
1 0 1 1 +/-1.0
CFG[13:12] Reserved DD[7], SDDREQ ICH6 internal 11.5K pull-downs
1 1 0 0 +/-0.25
CFG[15:14] Reserved
1 1 0 1 +/-0.5 LAN_CLK ICH6 internal 100K pull-downs
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 1 1 1 0 +/-0.75
CFG17 Global R-comp Disable 0 = All R-comp Disable 1 1 1 1 +/-1.0
(All R-comps) 1 = Normal Operation (Default)
3 CFG18 VCC Select 0 = 1.05V (Default) ICH7M IDE Integrated Series 3
C
1 = 1.5V
CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane PCI Routing Termination Resistors
Numbered in order
DD[15:0], DIOW#, DIOR#, DREQ,
1 =Reverse Lane,4->0,3->1 ect... IDSEL IRQ REQ/GNT approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#,
CFG20 SDVO/PCIE 0 = Only SDVO or PCIE x1 is
Concurrent operational (Default) R5C832 25 0 DCS3#, IDEIRQ
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
M
SDVOCRTL SDVO Present 0 = No SDVO device present (Default)
_DATA 1= SDVO device present
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
History
ITP Debug Conn. 1D05V_S0
2
N 2
1
1
1
11.18.2004: mini card not ready R72 R66
54D9R2F-L1-GP R68 39D2R2F-L-GP
54D9R2F-L1-GP CN1
29
2
2
2
4 XDP_TDI 1
4 XDP_TMS 2
4 XDP_TRST# 3
4
4 XDP_TCK 5
R69 22D6R2F-L1-GP 6
4 XDP_TDO 1 DY 2 TDO_FLEX# 7
3 CLK_XDP# CLK_XDP# 8
3 CLK_XDP CLK_XDP 9
10
XDP_TCK 11
4,6 H_CPURST# 1 DY 2 RESET_FLEX# 12
R71 22D6R2F-L1-GP 13
4 XDP_BPM#5
14
1
1
4 XDP_BPM#4 15
R67 R70 16
680R2J-3-GP 27D4R2F-L1-GP 3D3V_S0 17
4 XDP_BPM#0
18
4 XDP_BPM#1 19
2
2
1
20
R73 21
220R2J-L2-GP 4 XDP_BPM#2
22
23
1 4 XDP_BPM#3
24 1
2
25
4,17 XDP_DBRESET#
26 Wistron Corporation
27 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1D05V_S0
28 Taipei Hsien 221, Taiwan, R.O.C.
1
30 DY
C105 Title
SCD1U16V2ZY-2GP MLX-CON28-U
ITP
2
DY
Size Document Number Rev
A3
KAI -1
Date: Thursday, April 13, 2006 Sheet 2 of 44
A B C D E
3D3V_S0 3D3V_S0 3D3V_S0
1 2 3D3V_APWR_S0 1 2 3D3V_48MPWR_S0 1 2 3D3V_CLKGEN_S0
R439 0R3-0-U-GP R171 0R3-0-U-GP R172 0R3-0-U-GP
1
1
1
1
1
1
1
1
1
1
1
1
C555
C334 C333 C331 C332 C351 C554 C310 C557 C312 C556 C553
SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
2
2
2
2
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
4
3D3V_S0 4
IN EN OUT
(3D3V_S0) (6218_PGOOD) (VTT_PWRGD#)
1
1
PCLK_FWH_1 33R2J-2-GP 2 1 R435 PCLK_FWH 31
R146 R149 H L H PCLK_PCM_1 2 1 PCLK_PCM 22
10KR2J-3-GP 10KR2J-3-GP PCLK_KBC_1 33R2J-2-GP 2 1 R434
33R2J-2-GP R432 PCLK_KBC 29
H/L : CPU_ITP/SRC10 X H Hi - Z SS_SEL
3D3V_48MPWR_S0
2
2
3D3V_APWR_S0 1016
ITP_EN FSA
SS_SEL 3D3V_CLKGEN_S0 CPU_SEL2_1 1 2 CPU_SEL2
H/L: 27MHz/96MHz CPU_SEL1 R546 2K2R2J-2-GP
1
1
PM_STPCPU# 17
R148 R147 CLK_EN# 34 CLK_CPU_BCLK_1 1 4 CLK_CPU_BCLK 4
10KR2J-3-GP 10KR2J-3-GP CLK_CPU_BCLK_1# 2 3 CLK_CPU_BCLK# 4
DY DY RN25 SRN33J-5-GP-U
U24 CLK_MCH_BCLK_1 1 4 CLK_MCH_BCLK 6
2
2
CPU_SEL0 2 CLK_MCH_BCLK_1#
65
54
49
30
36
40
18
12
27
32
33
34
41
23
45
24
39
1 2 3 CLK_MCH_BCLK# 6
1
7
2K2R2J-2-GP R426 RN23 SRN33J-5-GP-U
VDDPCI
VDDPCI
VDDA
USB_48MHZ/FSLA
FSLB/TEST_MODE
VDDREF
VDD48
PCICLK1
PCICLK2
PCICLK3
CPU_STOP#
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDDCPU
PCICLK4/FCTSEL1
REF0/FSLC/TEST_SEL
VTT_PWRGD#/PD
17 CLK48_ICH R423 2 1 33R2J-2-GP FSA
PEG_REFCLKP_1 2 3 PEG_REFCLKP 38
3D3V_S0