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1 1




Compal Confidential
2 2




Churchill 13.3" M/B Schematics Document
Intel Arrandale SFF Processor with DDRIII + Ibex Peak-M



3 2010-03-31 3




REV:0.1




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/3/31 Deciphered Date 2011/3/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6411P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 31, 2010 Sheet 1 of 43
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A B C D E




Compal Confidential
Fan Control
page 4
Memory BUS(DDRIII)
Model Name : PAU10 Dual Channel 204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3 page 10,11
File Name : LA-6411P 1.5V DDRIII 800/1066/1333
Clock Generator Intel
1
6.4G/8.5G/10.6G 1
IDT: 9LRS3199AKLFT 100M/133M/166M(CFD)
SILEGO: SLG8SP587 Arrandale SFF
133/120/100/96/14.318MHZ to PCH
48MHZ to CardReader
page 12
Processor
USB port1,9
BGA1288 USB conn x 2
page 27


page 4,5,6,7,8,9


FDI x8 DMI x4

100MHz 100MHz USB port10
2.7GT/s 1GB/s x4 Camera
page 22
2 2
LCD Conn. LVDS
USB port12
page 30 Intel USB 2.0 Mini Card-2 SIM CONN
3.3V 48MHz page 28 page 25
WWAN
HDMI Conn. HDMI HDMI
Ibex Peak-M
page 24 Level shift PCH HD Audio DMIC
page 24 PCI-Express x 8 (PCIE1 2.5GT/S) 100MHz page 22
3.3V 24MHz
Audio CKT
port 3 port 2 ALC269Q-VB Audio Jack / Speaker
page 23 page 23
MINI Card -1 LAN(GbE)
WLAN BGA 1071pins
Realtek RTL8111E
w/ Bluetooth
page 28 page 26
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
100MHz port 0 SATA HDD Conn.
page 19
3
RJ45 page 13,14,15,16,17 3

page 35 18,19,20,21

RTC CKT. SPI
page 36
LPC BUS SPI ROM(SYS)
33MHz
TPM
Power On/Off CKT. page 13
page 40 page 32
ENE KB926 E0
page 29
ALS
DC/DC Interface CKT.
page 30
page 44,45
Int. KBD
page 30
Power Circuit DC/DC Power OK CKT. Touch Pad
4
page 30
CONN.page 30 SPI ROM(EC) 4

page 46~58
page 29



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/3/31 Deciphered Date 2011/3/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6411P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 31, 2010 Sheet 2 of 43
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( O MEANS ON X MEANS OFF ) Symbol Note :
Voltage Rails
+RTCVCC B+ +5VALW +1.5V +5VS
+3VALW +3VS : means Digital Ground
+1.5VS
power
1 plane +VGFX_CORE 1

+VCCP : means Analog Ground
+CPU_CORE
+1.05VS
+1.8VS
+0.75VS @ : means just reserve , no build
State +1.5V_CPU CONN@ : means ME part.



S0
O O O O O
S3 / DC
O O O O X Install below 45 level BOM structure for ver. 0.1
S3 / AC 45@ : means just put it in the BOM of 45 level.
O O O O X
S5 S4/AC
2 O O O X X 2



S5 S4/ Battery only
O O X X X
S5 S4/AC & Battery
don't exist
O X X X X


Install below 43 level BOM structure for ver. 0.1


SMBUS Control Table



3
SOURCE BATT SODIMM CLKGEN G-SENSOR 3



SMB_EC_CK1
SMB_EC_DA1
EC
V X X V
SMBCLK
SMBDATA
Calpella X V V X
SML1CLK
SML1DATA
Calpella X X X X




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/3/31 Deciphered Date 2011/3/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6411P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 31, 2010 Sheet 3 of 43
A B C D E
1 2 3 4 5




Layout rule 10mil width trace
length < 0.5", spacing 20mil
U1B +VCCP
20_0402_1% 1 2 R1 H_COMP3 AD71 REV1.0
COMP3 CLK_CPU_BCLK PM_EXTTS#0R2
BCLK AK7 CLK_CPU_BCLK 18 1 2 10K_0402_5%




Misc
20_0402_1% 1 2 R3 H_COMP2 AC70 AK8 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# 18 PM_EXTTS#1R4 1 2 10K_0402_5%
49.9_0402_1% 2 R5 H_COMP1 CLK_CPU_XDP




Clocks
1 AD69 K71 T1
COMP1 BCLK_ITP CLK_CPU_XDP#
J70 T2
49.9_0402_1% H_COMP0 BCLK_ITP#
1 2 R6 AE66
COMP0
A CLK_CPU_DMI DDR3 Compensation Signals A
PEG_CLK L21 CLK_CPU_DMI 14
J21 CLK_CPU_DMI#
PEG_CLK# CLK_CPU_DMI# 14
M71 PROC_DETECT
DPLL_REF_SSCLK Y2
W4 Support integrated graphics but without eDP, SM_RCOMP0 R7 1 2 100_0402_1%
H_CATERR# DPLL_REF_SSCLK# Can be connected to GND directly. SM_RCOMP1 R8
N61 1 2 24.9_0402_1%
CATERR# SM_RCOMP2 R9 1 2 130_0402_1%




Thermal
BJ12 SM_DRAMRST#
H_PECI SM_DRAMRST#
18 H_PECI N19
PECI SM_RCOMP0 Layout Note:Please these
BV33
SM_RCOMP[0] SM_RCOMP1 resistors near Processor
SM_RCOMP[1] BP39
to power; PU to VCCP at power side also BV40 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2]
N67




DDR3
Misc
29 H_PROCHOT# PROCHOT#
AV66 PM_EXTTS#0 T3
from DDR
PM_EXT_TS#[0] PM_EXTTS#1
PM_EXT_TS#[1] AV64 1 R10 2 PM_EXTTS#0_1 10,11
0_0402_5%
18 H_THERMTRIP# 1 R11 2 H_THERMTRIP#_R N17 THERMTRIP#
Processor Pullups
0_0402_5%
+VCCP
U71 XDP_PRDY# T4
PRDY# XDP_PREQ#
PREQ# U69
H_CATERR# R12 1 2 49.9_0402_1%
H_CPURST# N70 T67 XDP_TCK H_PROCHOT# R13 1 2 68_0402_5%
RESET_OBS# TCK XDP_TMS H_CPURST# R14 @
TMS N65 1 2 68_0402_5%




Power Management
15 H_PM_SYNC 1 R15 2 H_PM_SYNC_R M17 P69 XDP_TRST#
0_0402_5% PM_SYNC TRST#
T69 XDP_TDI
TDI XDP_TDO
TDO T71




JTAG & MBP
P71 XDP_TDI_M
TDI_M
1 R16 2 VCCPWRGOOD_1 AM7 T70
0_0402_5% VCCPWRGOOD_1 TDO_M
B
DBR# W71 XDP_DBRESET#
XDP_DBRESET# 15
5 +3VALW
C1 3
B
H_CPUPWRGD 1 R17 2 VCCPWRGOOD_0 Y67
18 H_CPUPWRGD VCCPWRGOOD_0 +1.5V
0_0402_5% 1 2
J69 XDP_BPM#0 T5
BPM#[0]
15 PM_DRAM_PWRGD 1 R18 2 PM_DRAM_PWRGD_R AM5 J67 XDP_BPM#1
T6
SM_DRAMPWROK BPM#[1] 0.1U_0402_16V7K




5




1
0_0402_5% J62 XDP_BPM#2 U2
BPM#[2] T7
K65 XDP_BPM#3 2 VCCP_POK R19 1 @ 2 0_0402_5% R20




P
BPM#[3] T8 B VCCP_POK 38
H_VTTPWRGD H15 K62 XDP_BPM#4 T9 4 1K_0402_5%
VTTPWRGOOD BPM#[4] XDP_BPM#5 Y Q1
J64 T10 1
BPM#[5]




G
XDP_BPM#6 A
K69 T11




2
BPM#[6]




S


D
T12 H_PWRGD_XDP 1 R21 2 H_PWRGD_XDP_R Y70 M69 XDP_BPM#7 SM_DRAMRST# 3 1 DIMM_DRAMRST#
T13




3
TAPPWRGOOD BPM#[7] DIMM_DRAMRST# 10,11




1
0_0402_5%




1
1 R22 2 BUF_PLT_RST#_R G3 NC7SZ08P5X_NL_SC70-5 BSH111_SOT23
17,26,28,29,32 PLT_RST# RSTIN#
1.5K_0402_1% R23




G
2
1.5K_0402_1% R24
1




100K_0402_5%




2




2
R25 AUBURNDALE SFF_BGA1288 PM_DRAM_PWRGD_R
750_0402_1%

6
2




1
VCCP_POK 1 R26 2 H_VTTPWRGD R27
1K_0402_1% 750_0402_1% RST_GATE
18 RST_GATE
1




2
R28 CPU for LOAD BOM
560_0402_5% C2
470P_0402_50V8J
2




U1 U1
+5VALW
From Power VCCP PWRGOOD




2
C C
R29
Celeron_U3400 I3-330UM 10K_0402_5%

U3400@ I3@
CPU XDP Signal




1
S3_0.75V_EN 37 +3VS




1
D
VCCP_POK 2 Q2 XDP_DBRESET# R30 1 2 1K_0402_5%
G SSM3K7002FU_SC70-3
S




3
+VCCP

PWM FAN XDP_TDO R31 1 2 51_0402_5%

XDP_PREQ# R32 1 @ 2 51_0402_5%
+5VS XDP_TMS R33 1 @ 2 51_0402_5%
R336
1 2 XDP_TDI R34 1 @ 2 51_0402_5%
0_0805_5%
1
C6 XDP_TRST# R35 1 2 51_0402_5%
10U_0805_10V4Z
2 XDP_TCK
40mil R36 1 @ 2 51_0402_5%
JFAN1
+5VS_FAN 1
EC_FAN_PWM R170 2 FAN_PWM_R 1
29 EC_FAN_PWM 1 2
2 G1
4
0_0402_5% 3 5
3 G2
ACES_85204-03001
D CONN@ D




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/3/31 Deciphered Date