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PJP1 PJP1
14W_DCIN 15W_DCIN
14W_45@ 15W_45@
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ZZZ1
PCB
Compal Confidential
2
JFWXX Schematics Document 2
Intel Merom Processor with SiSM672MX + DDRII + SiS968 + SiS307LV
2007-09-06
3
REV: 0.3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JFWXX M/B LA-3961P Schematic
Date: Thursday, September 06, 2007 Sheet 1 of 49
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Compal Confidential
Thermal Sensor Clock Generator
Model Name : JFWXX Fan Control Intel Merom Processor
page 4 ADM1032 ICS9LPRS600C+
page 4
File Name : LA-3961P uPGA-478 Package ICS9P935
page 14,15
1
page 4,5,6 1
FSB
H_A#(3..35) 667/800MHz H_D#(0..63)
CRT & TV-out
page 17
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
SiS M672MX
Single Channel BANK 0, 1, 2, 3 page 12,13
PCI-Express
LCD Conn. SiS 307LV TEBGA-847 1.8V DDRII 533/667
page 17 page 18
page 7,8,9,10,11
1GB/s MuTIOL IO Link USB conn x2 USB conn x2 Bluetooth Web Camera
TO M/B TO I/O/B Conn page
page 33 page 37 33 page 37
2 2
PCI-Express USB
3.3V 48MHz
SiS968
3.3V 24.576MHz/48Mhz HD Audio
MII
3.3V ATA-100 IDE
PCI BUS TEBGA-570
S-ATA port 0
page 19,20,21,22,23
3.3V 33 MHz
New Card MINI Card x1 CDROM MDC 1.5 HDA Codec
IDSEL:AD22
Socket WLAN LAN (PIRQG#,PIRQH#, Conn. 24
page
Conn 37
page
ALC268
page 35
page 30 GNT#0, REQ#0)
page 29 page 28
S-ATA HDD
Card Reader Conn.page 24
R5C833
page 26 Audio AMP
RJ45 page 36
3
page 28 LPC BUS 3
13 94 3 in 1
Conn. socket
page 26 page 27
RTC CKT.
page 20 ENE KB926
page 31
Power On/Off CKT. Switch/B Conn.
page 34
page 32
Touch Pad Int.KBD
page 33 page 32
DC/DC Interface CKT.
I/O Conn. BIOS
page 40
page 33
FRONT LCD /B.
Power Circuit DC/DC LID SW
4 4
page 41,42,44,458
46,47,48 page 34
CHARGER Security Classification Compal Secret Data Compal Electronics, Inc.
page 43
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JFWXX M/B LA-3961P Schematic
Date: Thursday, September 06, 2007 Sheet 2 of 49
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Voltage Rails
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Power Plane Description S1 S3 S5
External PCI Devices
1
VIN Adapter power supply (19V) N/A N/A N/A DEVICE IDSEL # REQ/GNT # PIRQ 1
B+ AC or battery power rail for power circuit. N/A N/A N/A
CARD BUS CB1410 AD20 2 C,D
+CPU_CORE Core voltage for CPU ON OFF OFF
1394+Cardreader AD22 0 G,H
+0.9VS ( Actual +0.9V ) 0.9V switched power rail for DDR terminator ON ON OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
EC SM Bus1 address EC SM Bus2 address
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF Device Address Device Address
+3VALW 3.3V always on power rail ON ON ON* Smart Battery 0001 011X b ADI ADM1032 1001 100X b
+3VS 3.3V switched power rail ON OFF OFF EEPROM(24C16/02) 1010 000X b NVIDIA NB8X
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON ICH8M SM Bus address
2 2
Device Address
Clock Generator 1101 001Xb
SIGNAL (ICS9LPRS325AKLFT_MLF72)
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
DDR DIMM0 1010 000Xb
Full ON HIGH HIGH HIGH HIGH ON ON ON ON DDR DIMM1 1010 010Xb
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
PROJECT ID Table
3 3
PROJECT_ID
SKU ID Table R311 R311 R311 R311 R311 R311
14W R424 (Pull low)
Vcc 3.3V +/- 5%
15W NA (Internal Pull High)
Ra 100K +/- 5%
8.2K_0402_5% 18K_0402_5% 33K_0402_5% 56K_0402_5% 100K_0402_5% 200K_0402_5%
14_B@ 14_C@ 14_MP@ 15_A@ 15_B@ 15_C@
Ra~ R312
Rb~ R311
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max Rb BOM Structure
0 0 0 V 0 V 0 V 14_A@
1 8.2K +/- 5% 0.217 V 0.250 V 0.288 V 14_B@
2 18K +/- 5% 0.439 V 0.503 V 0.575 V 14_C@
3 33K +/- 5% 0.721 V 0.819 V 0.926 V 14_MP@
4 56K +/- 5% 1.054 V 1.185 V 1.325 V 15_A@
5 100K +/- 5% 1.489 V 1.650 V 1.819 V 15_B@
6 200K +/- 5% 2.019 V 2.200 V 2.386 V 15_C@
4 4
7 NC 3.135V 3.300 V 3.465 V 15_MP@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JFWXX M/B LA-3961P Schematic
Date: Thursday, September 06, 2007 Sheet 3 of 49
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5 4 3 2 1
H_A#[3..35] Trace length must short Place close to CPU within 500mil
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
JP36A
H_RS#[0..2] H_A#3 J4 H1 +1.05VS
<7> H_RS#[0..2] A[3]# ADS# H_ADS# <7>
ADDR GROUP 0
H_A#4 L5 E2 H_BNR# <7>
H_A#5 A[4]# BNR#
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5 Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount) H_PREQ# R85 1 2 @ 56_0402_5%
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 H_IERR# R115 1 2 56_0402_5%
A[8]# DRDY# H_DRDY# <7>
D H_A#9 J1 E1 D
A[9]# DBSY# H_DBSY# <7>
H_A#10 N3 Intel :Pull-up 56ohm (Mount) SiS : Pull-up 54.9ohm (Mount) ITP_TMS R84 1 2 56_0402_5%
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 ITP_TDI R83 1 2 150_0402_1%
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT# H_PROCHOT# R113 1 56_0402_5%
H_A#15
P4 A[14]# INIT# B3 H_INIT# <20> Intel :Pull-up 56ohm (Mount) SiS : Pull-up 75ohm (Mount) 2
P1 A[15]#
H_A#16 R1 H4 H_LOCK# <7> ITP_TCK R69 1 2 27.4_0402_1%
A[16]# LOCK#
<7> H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# <7> ITP_TRST# R61 1 2 680_0402_5%
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# <7> Checklist recommend 39 Ohm CRB pull 75 Ohm
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4
H_A#18
H_A#19
U5
R3
A[17]#
A[18]#
HITM#
AD4
H_HITM# <7>
ADM1032 +3VS
A[19]# BPM[0]#
ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 AD1
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# C112 1
Y5 A[22]# BPM[3]# AC4 2 0.1U_0402_16V4Z
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# H_PREQ#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 ITP_TCK
H_A#26 A[25]# TCK ITP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 1 U7
H_A#28 A[27]# TDO ITP_TMS C111
W5 A[28]# TMS AB5 1 VDD SCLK 8 EC_SMB_CK2 <31>
H_A#29 Y4 AB6 ITP_TRST#
C H_A#30 A[29]# TRST# ITP_DBRESET# 2200P_0402_50V7K THERMDA C
U2 A[30]# DBR# C20 ITP_DBRESET# 2 D+ SDATA 7 EC_SMB_DA2 <31>
H_A#31 2
V4 A[31]#
H_A#32 W3 THERMDC 3 6
H_A#33 A[32]# H_PROCHOT# D- ALERT#
AA4 A[33]# THERMAL H_PROCHOT# <20>
H_A#34 AB2 Connect SB SYS_RESET# or just left NC 4 5
H_A#35 A[34]# THERM# GND
AA3 A[35]# PROCHOT# D21
V1 A24 THERMDA
<7> H_ADSTB#1 ADSTB[1]# THERMDA
B25 THERMDC ADM1032ARMZ_MSOP8
H_A20M# THERMDC
<20> H_A20M# A6 A20M#
ICH
H_FERR# A5 C7 H_THERMTRIP# H_THERMTRIP# <20> F75383M_MSOP8
<20> H_FERR# FERR# THERMTRIP#
H_IGNNE# C4 C114 1 2 0.1U_0402_16V4Z
<20> H_IGNNE# IGNNE#
H_STPCLK# D5
<20> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<20> H_INTR LINT0
H_NMI B4 A22
<20> H_NMI LINT1 BCLK[0] H_CLK_DP0 <14>
H_SMI# A3 A21
<20> H_SMI# SMI# BCLK[1] H_CLK_DN0 <14>
M4
N5
RSVD[01] FAN1 Conn
RSVD[02]
T2 RSVD[03]
V3 RSVD[04]
B2
RESERVED
RSVD[05]
C3 RSVD[06]
D2 RSVD[07]
D22 RSVD[08] +5VS
D3 RSVD[09] H_THERMDA, H_THERMDC routing together, +5VS
F6 RSVD[10] Trace width / Spacing = 10 / 10 mil C58 1 2 10U_0805_10V4Z
1
B B
Merom Ball-out Rev 1a U3 D12
conn@ 1 8
VEN GND 1SS355_SOD323
2 VIN GND 7
+VCC_FAN1 3 6
2
EN_FAN1 VO GND D11
<31> EN_FAN1 4 VSET GND 5
1 2
G993P1UF_SOP8
BAS16_SOT23-3
C52 10U_0805_10V4Z
+1.05VS 1 2
CPU to SB interface +3VS C55
R120 1 2 56_0402_5% H_STPCLK# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 1000P_0402_50V7K
1 2
1
R141 1 2 56_0402_5% H_INIT# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) R31
R128 1 2 56_0402_5% H_IGNNE# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 10K_0402_5% 40mil
R144 1 JP6
2 56_0402_5% H_SMI# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
2
+VCC_FAN1 1
R148 1 1
2 56_0402_5% H_A20M# Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) <31> FAN_SPEED1 2 2
3 3
R137 1 2 56_0402_5% H_NMI Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 1
C54 4
R140 1 GND
2 56_0402_5% H_INTR Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount) 5 GND
1000P_0402_50V7K
R127 1 2
A 2 56_0402_5% H_THERMTRIP# Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount) ACES_85205-03001