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Digitally signed by dd
KEYLARGO-Integrate VER : 2A
01
DN: cn=dd, o=dd, ou=dd
[email protected]
c=US
A Date: 2009.11.30 17:33:02 A
+07'00'
DC/DC
AC/BATT CPU VR CLOCKS Thermal RESET CKT
RUN POWER SW CONNECTOR
PG 45 Yonah +3V_SRC
+5VSUS Monitor
PG 3,4
PG 33 PG 38
BATT PG 41,42,43 PG 40 PG 17
PG 44 PG 39 (478 Micro-FCPGA)
CHARGER
LVDS Panel Connector
PG 19
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533/667 MHz FSB
VGA Daughter TVOUT
400/533/667 MHZ DDR II Connector CRT
DDR-SODIMM1 PG 18
B
PG 15,16 Calistoga B
TVOUT S-Video
400/533/667 MHZ DDR II PG 5,6,7,8,9,10 PG 20
DDR-SODIMM2
PG 15,16 1466 uFCBGA CRT CRT
PCI-Express Grapfic PG 20
USB2.0 (P4,P6)
2 Back side PG 30
SATA - HDD SATA DMI interface USB2.0 (P0,P2)
2 Right Side PG 30
PG 24
BCM4401 RJ45/Magnetics
IDE
Fixed Odd PG 37
PG 36
PG 24 ICH7-M
AC97/Azalia 652 BGA 33MHz PCI
C
5 in 1 C
Card/1394 1394 Conn.
PG 11,12,13,14 R5C832
AUDIO MDC PG 22
PG 21,23
PG 34 PG 27
USB2.0 (P1,P5)
LPC
PCIEx2
Audio Tip
Jacks Ring Mini-Card
SIO ECE5011 WLAN
PG 35 PG 27 SIO MEC5004
Expander USB2.0 (P7) EXPRESS-CARD
128KB Flash SMB Bluetooth
USB 2.0
SPI TMKBC
Hub(4) PG 27 PG 25,26
128 Pins VTQFP
128 Pins VTQFP
SPI
PG 28 PG 29
D D
PS/2
QUANTA
Flash Keyboard Touch pad
Title
COMPUTER
PG 30 PG 28 PG 32 Schematic Block Diagram1
Size Document Number Rev
FM1 2A
Date: Tuesday, September 06, 2005 Sheet 1 of 51
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX
02
Power & Ground
Pg# Description DNI LIST
Label Pg# Description Control Signal
1 Schematic Block Diagram 1
DC_IN+ AC ADAPTER (20V)
2 Blank Page
PBATT+ MAIN BATTERY + (10~17V)
3 Front Page
A
PWR_SRC MAIN POWER (10~20V) A
4-5 Dothan
RTC_PWR3_3V RTC & PCL POWER (3_3V)
6-10 Alviso
+12V +12V DRUNPWROK
11-13 ICH6
VHCORE CPU CORE POWER (1.25/1.15V) RUNPWROK
14-15 DDRII SO-DIMM(200P)
V1_2RUN AGTL+ POWER (1.2V) RUNPWROK
16 Clock Generator
17 CH7306/7
+3VRUN SLP_S3# CTRLD POWER RUN_ON
18-19 Blank Pages
+3VSUS SLP_S5# CTRLD POWER SUS_ON
20 LCD Conn. & SSP
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+5VALW 8051 POWER (5V)
21 CRT & TV Conn.
+5VRUN SLP_S3# CTRLD POWER RUN_ON
22 SATA & IDE Conn.
+5VSUS SLP_S5# CTRLD POWER SUS_ON
23 Screw Hole
B B
+5VHDD HDD POWER (5V) HDDC_EN#
24 TI PIC6515
+5VMOD MODULE POWER (5V) MODC_EN#
25 Mini PCI Conn.
STRB#/5V EXTERNAL FDD POWER (5V) FDD/LPT#
26 MDC Conn.
+5VFAN1, +5VFAN2 FAN POWER (5V) FAN_OFF/ON#
27-28 SIO (LPC47N354)
VDDA AUDIO ANALOG POWER (5V) RUN_ON
29 SERIAL PORT & USB
1_8VSUS RESUME WELL IN ICH
30 PARALLEL CONN.
1_8VRUN SLP_S3# CTRLD POWER
31 Flash ROM
+3VALW 8051 POWER (3V)
32 TOUCH PAD & BLUE TOOTH
V1_5RUN AGP I/O POWER
33 Switch Board Conn. & LED
34 FAN & Thermal
GND ALL PAGES DIGITAL GROUND
C
35-36 Audio CODEC (STAC9751) & Phone Jack C
37-38 LOM (BCM5751), Switch
39 FIR GNDP CPU POWER GND
40-41 Docking Conn. & Q-Switch
CGNDP CHARGER GND
42 Power Good
43-44 Battery Selector & Charger DGNDP DC/DC POWER GND
45 CPU Power LANGND COMBO CONN GND
46 1.8V,0.9V,1.5V,1.05V
47 3VALW/5V/3V/Power ON
48 RUN Power Switch
49 VGA DC/DC
D D
50 DCIN/Batt Conn.
QUANTA
Title
COMPUTER
Index, DNI, Power & Ground
Size Document Number Rev
FM1 2A
Date: Tuesday, September 06, 2005 Sheet 2 of 51
1 2 3 4 5 6 7 8
A B C D E
5 H_A#[3..31]
H_A#[3..31]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
J4
L4
M3
K5
U10A
A[3]#
A[4]#
A[5]#
A[6]#
ADS#
BNR#
BPRI#
H1
E2
G5
H_ADS#
H_BNR#
H_BPRI#
5
5
5
5 H_D#[0..63]
H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
E22
F24
E26
H22
U10B
D[0]#
D[1]#
D[2]#
D[3]#
D[32]#
D[33]#
D[34]#
D[35]#
AA23
AB24
V24
V26
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#[0..63]
H_D#[0..63] 5
03
DATA GRP 0
M1 H5 F23 W25
DATA GRP 2
H_A#8 A[7]# DEFER# H_DEFER# 5 H_D#5 D[4]# D[36]# H_D#37
ADDR GROUP 0
N2 A[8]# DRDY# F21 H_DRDY# 5 G25 D[5]# D[37]# U23
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
H_A#10 A[9]# DBSY# H_DBSY# 5 H_D#7 D[6]# D[38]# H_D#39
N3 E23 U22
CONTROL
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 F1 H_BR0# 5 K24 AB25
H_A#12 A[11]# BR0# H_D#9 D[8]# D[40]# H_D#41
P2 G24 W22
H_A#13 A[12]# H_IERR# H_D#10 D[9]# D[41]# H_D#42
L1 D20 J24 Y23
1 H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43 1
P4 B3 H_INIT# 11 J23 AA26
H_A#15 A[14]# INIT# H_D#12 D[11]# D[43]# H_D#44
P1 H26 Y26
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 H4 H_LOCK# 5 F26 Y22
A[16]# LOCK# H_D#14 D[13]# D[45]# H_D#46
5 H_ADSTB#0 L2 K22 AC26
ADSTB[0]# H_D#15 D[14]# D[46]# H_D#47
B1 H_RESET# 5 H25 AA24
RESET# D[15]# D[47]#
5 H_REQ#0 K3 F3 H_RS#0 5 5 H_DSTBN#0 H23 W24 H_DSTBN#2 5
REQ[0]# RS[0]# DSTBN[0]# DSTBN[2]#
5 H_REQ#1 H2 F4 H_RS#1 5 5 H_DSTBP#0 G22 Y25 H_DSTBP#2 5
REQ[1]# RS[1]# DSTBP[0]# DSTBP[2]#
5 H_REQ#2 K2 G3 H_RS#2 5 5 H_DINV#0 J26 V23 H_DINV#2 5
REQ[2]# RS[2]# DINV[0]# DINV[2]#
5 H_REQ#3 J3 G2 H_TRDY# 5
REQ[3]# TRDY# H_D#[0..63] H_D#[0..63]
5 H_REQ#4 L5 5 H_D#[0..63] H_D#[0..63] 5
H_A#[3..31] REQ[4]# H_D#16 H_D#48
5 H_A#[3..31] G6 H_HIT# 5 N22 AC22
H_A#17 HIT# H_D#17 D[16]# D[48]# H_D#49
Y2 A[17]# HITM# E4 H_HITM# 5 K25 D[17]# D[49]# AC23
H_A#18 U5 H_D#18 P26 AB22 H_D#50
H_A#19 A[18]# ITP_BPM0# H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AA21
H_A#20 ITP_BPM1# H_D#20 H_D#52
DATA GRP 1
W6 AD3 L25 AB21
DATA GRP 3
H_A#21 A[20]# BPM[1]# ITP_BPM2# H_D#21 D[20]# D[52]# H_D#53
U4 AD1 L22 AC25
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ITP_BPM3# H_D#22 D[21]# D[53]# H_D#54
Y5 A[22]# BPM[3]# AC4 L23 D[22]# D[54]# AD20
H_A#23 U2 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
H_A#24 A[23]# PRDY# ITP_BPM#5 H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 ITP_TCK H_THERMDA & H_THERMDC H_D#25 P22 AD24 H_D#57
H_A#26 A[25]# TCK ITP_TDI +1.05V_VCCP H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 trace routing W:10/S:10 P23 D[26]# D[58]# AE21
H_A#27 ITP_TDO H_D#27 H_D#59
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W3 A[27]# TDO AB3 T24 D[27]# D[59]# AD21
H_A#28 W5 AB5 ITP_TMS H_D#28 R24 AE25 H_D#60
H_A#29 A[28]# TMS ITP_TRST# H_D#29 D[28]# D[60]# H_D#61
Y4 A[29]# TRST# AB6 L26 D[29]# D[61]# AF25
H_A#30 W2 C20 ITP_DBRESET# H_D#30 T25 AF22 H_D#62
H_A#31 A[30]# DBR# H_D#31 D[30]# D[62]# H_D#63
Y1 A[31]# N24 D[31]# D[63]# AF26
5 H_ADSTB#1 V4 ADSTB[1]# PROCHOT D21 CPU_PROCHOT# R158
5 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 5
A24 1K/F_0402 N25 AE24
THERMDA H_THERMDA 33 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
11 H_A20M# A6 A20M#
THERM THERMDC A25 H_THERMDC 33 5 H_DINV#1 M26 DINV[1]# DINV[3]# AC20 H_DINV#3 5
11 H_FERR# A5 FERR#
Place voltage
C4 C7 divider within V_CPU_GTLREF AD26 R26 COMP0
11 H_IGNNE# IGNNE# THERMTRIP# H_THERMTRIP# 33 GTLREF COMP[0] COMP1
0.5" of GTLREF MISC COMP[1] U26
2 COMP2 2
11 H_STPCLK# D5 STPCLK# pin COMP[2] U1
C6 TEST1 C26 V1 COMP3
11 H_INTR
H CLK
LINT0 R160 R113 1K_NC TEST1 COMP[3]
11 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 17
A3 A21 2K/F_0402 TEST2 D25 E5
11 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17 TEST2 DPRSTP# H_DPRSTP# 11,40
R114 51_0402 B5
DPSLP# H_DPSLP# 11
AA1 RSVD[01]# DPWR# D24 H_DPWR# 5
AA4 RSVD[02]# RSVD[12]# T22 6,17 CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 11
AB2 6,17 CPU_BSEL1 B23 D7 H_CPUSLP# 5,11
RSVD[03]# BSEL[1] SLP#
2
2
2
2
AA3 C21 AE6