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V6J SCHEMATIC V2.0
1 1
PAGE Content PAGE Content
SYSTEM PAGE REF. POWER PAGE REF.
4 YONAH CPU-1 45 POWER ON SEQUENCE
5 YONAH CPU-2 46 DISCHARGE & HOLES & EMI
6 CPU CAP & THERMAL SENSOR 47 POWER_VCORE
7 Calistoga: CPU 48 POWER_SYSTEM
8 Calistoga: DDR2 & DMI & PCIE 49 POWER_I/O_1.5VS & 1.05VS
9 Calistoga: DDR2 50 POWER_I/O_DDR & VTT
10 Calistoga: POWER & Caps 51 POWER_I/O_+3VAO & +2.5VS
11 Calistoga: GND & NCTF 52 POWER_VGA_CORE & RAM
2 12 Calistoga: Straps 53 POWER_+1.2VSP 2
13 CLOCK: ICS954310 54 POWER_CHARGER
14 DDR2 SODIMM (0) & Caps 55 POWER_PIC
15 DDR2 SODIMM (1) & Caps 56 POWER_SELECTOR
16 DDR2 TERMINATOR 57 POWER_PROTECT
17 G72M: PCIE 58 POWER_LOAD SWITCH
18 G72M: FB 59 POWER_FLOWCHART
19 G72M: VRAM 60 POWER_SIGNAL
20 G72M: RGB/LCD/ROM/GPIO
21 G72M: MIOB/CRSTAL/TMDS
22 LVDS & INVERTER CONNECTOR
3
23 CRT & LID SW & TPM CONNECTOR 3
24 ICH7: IDE & LPC & RTC & AC97
25 ICH7: PCI & INT & USB & DMI
26 ICH7: SMB & PWR & CLK & GPIO
27 ICH7: PWR & Caps
28 HDD & ODD CONNECTOR
29 USB CONNECTOR
30 SIO: LPC47N207
31 FIR & FWH
32 KBC: M38857
33 AUDIO AD1986A
34 AUDIO AMP GMT01420 & JACK
4 35 MIC AMP 4
36 SMBUS & POWER CONNECTION
37 GIGA LAN: REALTEK 8111B
38 LAN TRANSFORMER & JACK & MDC
39 MINI Card
40 RICOH: R5C832
41 NEWCARD
42 4 IN 1 MEMORY CARD & 1394
43 FAN CONTROLLER & DC IN
44 INSTANT KEY & TP BRD & SW FPC
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REVISION DATE: Friday, November 25, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: V6J 2.0 SHEET 1 OF 63 Content & History RELEASE DATE : Feng Lin
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V6J: YONAH/Calistoga/G72M BLOCK DIAGRAM
CRT BOARD BATTERY DC JACK BOARD
1
2 TYPE SWITCH FPC 1
CRT 4 X 1 & FUNCTION KEY & BUT RJ45 DC
4 X 2 & LEDs JACK JACK
?? 38
62
YONAH CPU
CLOCK GEN. 479 uFCPGA
CAP/RES
ICS954310 4,5 .... 6 RESET SM_BUS
13 45 36
2 LVDS &
HOST BUS 2
INV. AGTL
22 1.05V,667MHZ
DDR DCIN
NVIDIA
PCI EXPRESS
X16 Calistoga DDR2 SDRAM 533/667MHz 533/667
DDR2
.... CAP/RES
16
RTC
FAN CON. 63
SODIMM X2
CRT CONN23 G72M 1466 uFCBGA
+1.8V
533 BGA +0.9VS 14,15
17,18,19,20,21 7,8,9,10,11,12 Thermal
Sensor
DMI x2 Max6657MSA
6
USB2.0
USB X4
3
29
ICH7-M PCIE_BUS 4X1, 2.5Gb/s
3
VCORE 47
IDE_BUS 652 mBGA
PCI_BUS 3.3V, 33MHz
SYSTEM 48 LAN 1G
AZALIA MINI Card
ODD 18,19,20,21 NEWCARD Realtek
Slave HDD 1 SLOT RTL8111b37 39
1.5VS Master28 4 IN 1
1.05VS 49
28 CARD CARDREAD 41
RICOH
READER R5C83240
42
CHARGE LPC, 33MHz RJ11 JACK
54 RJ45 CONN
LAN IO
38 38
AZALIA MDC CONN. 1394
PIC16C54 55 CODEC SLOT
4 4
AD1986A33 38 42
SUPER I/O KEYBOARD
BATLOW/SD# 52 47N207 30 CONTROLLER FWH
M3885XHP 32 31
AUDIO AMP
G1420
LOAD Switch 34
58
FIR
VGA VCORE INTERNAL
RAM 52
31
KEYBOARD
32
TOUCHPAD BOARD
SPDIF
+3VAO 34 LEDs LID TP
+2.5VS 51
42
5 MIC AMP 5
NJM2100 MIC IN
35 34
REVISION DATE: Friday, November 25, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: V6J 2.0 SHEET 2 OF 63 BLOCK DIAGRAM RELEASE DATE : Feng Lin
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PCI Device IDSEL# REQ/GNT# Interrupts PC/PCI
AZALIA : PCI_INTB#
Chipset (Host to PCI) (AD30 internal) n/a USB 0,1 : PCI_INTA#
Mini_PCI AD18 3 B,D USB 2,3 : PCI_INTD#
LAN --88E8001 AD16 0 B USB 4,5 : PCI_INTC#
CardBus AD17 1 B
1
1394 AD17 1 A CLK = 1101001x ( D2 ) 1
4 IN 1 1 C SMBUS ADDRESS : DDR_SODIMM0 = 1010010x ( A4 )
DDR_SODIMM1 = 1010000x ( A0 )
THERMAL = 1001100x ( 98 )
ICH7M_GPIO Use As Signal Name Power TPM = TBD
GPIO00 GPI PM_BMBUSY# +3VS
GPIO01 GPI PCI_REQ#5 +3VS
GPIO02 GPI G72M_THRM#(reserve) +3VS
GPIO[3:5] GPI PCI_INT[E:H] +3VS M38857_GPIO Use As Signal Name
GPIO06 GPO BACK_OFF# +3VS P20 GPO KBCRSM
G72M_GPIO Use As Signal Name
GPIO07 GPI WIRLESS_# +3VS P21 GPI
GPIO00 GPI
GPIO08 GPI EXTSMI#_3A +3VSUS P22 GPO BAT_LEARN
2 GPIO01 GPI 2
GPIO09 GPI ACIN_OC_ICH(reserve) +3VSUS P23 GPO CPPE_EN
GPIO02 GPO
GPIO10 GPI CHG_FULL_OC +3VSUS P24 GPO SET_PCIRSTNS#
GPIO03 GPO LCD_VDD_EN#
GPIO11 NATIVE SMBALERT# +3VSUS P25 GPO CAP_LED#
GPIO04 GPO LCD_BACKEN
GPIO12 GPI KBCSCI_3 +3VSUS P26 GPO NUM_LED#
GPIO05 GPO
GPIO13 GPI BATIN_OC#_ICH(reserve) +3VSUS P27 GPO SCROLL_LED#
GPIO06 GPO
GPIO14 GPO LID_ICH#_3A(reserve) +3VSUS P40 GPO KBC_EXTSMI
GPIO07 GPO
GPIO15 GPI 802_LED# +3VSUS P41 GPO PANLOCK_LED#
GPIO08 GPI GPIO8/ALERT#
GPIO16 GPO PM_DPRSLPVR +3VSUS P42 GPO WATCHDOG
GPIO09 GPO
GPIO17 GPO PCI_GNT#5 +3VSUS P43 GPO CHG_FULL_KBC(reserve)
GPIO10 GPIO G72M_GPIO12
GPIO18 GPO STP_PCI# +3VSUS P44 GPO KBDCPURST_3Q
GPIO11 GPO
GPIO19 GPI SATA_DET_#1 +3VSUS P45 GPO KBC_GA20
GPIO12 GPO
3 GPIO20 GPO STP_CPU# +3VS P46 GPO KBSCI_3Q 3
GPIO21 GPI BATSEL_2P(reserve) +3VS P47 GPI PM_CLKRUN#
47N207_GPIO Use As Signal Name
GPIO22 NATIVE PCI_REQ#4 +3VS P50 GPI BAT_LOW#_KBC
GP10 GPIO
GPIO23 NATIVE LDRQ1# +3VS P51 GPO
GP11 GPIO
GPIO24 GPO +3VSUS P52 GPI KBDDT0
GP12 GPO
GPIO25 GPO +3VSUS P53 GPI KBDDT1
GP13 GPO
GPIO26 GPO OP_SD# +3VSUS P54 GPI LID_ICH#_3A
GP14 GPO FIR_SEL
GPIO27 GPO WLAN_ON +3VSUS P55 GPI BAT_IN#_OC
GP15 GPIO PWR_THRO#
GPIO28 GPO PWR_1HZ +3VSUS P56 GPO FAN_DA
GP16 GPIO ODD_DIS#
GPIO29 NATIVE USB_OC#45 +3VSUS P57 GPO ADJ_BL
GP17 GPIO RST#_XCARD
GPIO30 NATIVE USB_OC#67 +3VSUS P60 GPI BLUETOOTH_#
GP30 GPIO PID0
GPIO31 NATIVE USB_OC#67 +3VSUS P61 GPI INTERNET#
4 GP31 GPIO 4
GPIO32 GPO PM_CLKRUN# +3VSUS P62 GPI CPPE#
GP32 GPIO G72M_THRO#
GPIO33 GPO BT_ON +3VS P63 GPI
GP33 GPIO CPUFAN_SPD_A
GPIO34 GPO FWH_WP# +3VS P64 GPI ACIN_OC
GP34 GPIO SW_RST#
GPIO35 GPO +3VS P65 GPI MARATHON_#
GP35 GPIO
GPIO36 GPO BT_LED# +3VS P66 GPI PANLOCK_#
GP36 GPIO
GPIO37 GPI PCB_VID0 +3VS P67 GPI
GP37 GPIO
GPIO38 GPI PCB_VID1 +3VS P76 GPI/O SMD_BAT
GPIO39 GPI PCB_VID2 +3VS P77 GPI/O SMC_BAT
GPIO[40:47] N/A N/A N/A
GPIO48 NATIVE FWH_TBL# +3VS
GPIO49 NATIVE H_PWRGD +3VS
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REVISION DATE: Friday, November 25, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: V6J 2.0 SHEET 3 OF 63 SYSTEM INFO. RELEASE DATE : Feng Lin
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5 4 3 2 1
H_D#[0..63] 7
7 H_A#[3..16] U1A
H_A#3 +VCCP U1B
J4 A[3]# ADS# H1 H_ADS# 7
H_A#4 L4 E2 H_D#0 E22 AA23 H_D#32
A[4]# BNR# H_BNR# 7 D[0]# D[32]#
H_A#5 M3 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 7 D[1]# D[33]#
H_A#6 K5 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# R1 H_D#3 D[2]# D[34]# H_D#35
M1 A[7]# DEFER# H5 H_DEFER# 7 H22 D[3]# D[35]# V26
ADDR GROUP 0
DATA GRP 2
H_A#8 N2 F21 56Ohm H_D#4 F23 W25 H_D#36
A[8]# DRDY# H_DRDY# 7 D[4]# D[36]#
DATA GRP 0
H_A#9 J1 E1 +VCCP H_D#5 G25 U23 H_D#37
H_A#10 A[9]# DBSY# H_DBSY# 7 D[5]# D[37]#
N3 H_D#6 E25 U25 H_D#38
H_A#11 A[10]# H_D#7 D[6]# D[38]# H_D#39
D P5 A[11]# BR0# F1 H_BR0# 7 E23 D[7]# D[39]# U22 D
1
H_A#12 P2 H_D#8 K24 AB25 H_D#40
H_A#13 A[12]# H_IERR# T1 R2 H_D#9 D[8]# D[40]# H_D#41
L1 D20 G24 W22
CONTROL
H_A#14 A[13]# IERR# 54.9Ohm H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# 24 J24 D[10]# D[42]# Y23
H_A#15 P1 /* H_D#11 J23 AA26 H_D#43
H_A#16 A[15]# H_D#12 D[11]# D[43]# H_D#44
1
R1 A[16]# LOCK# H4 H_LOCK# 7 H26 D[12]# D[44]# Y26
H_D#13 H_D#45
2
7 H_ADSTB#0 L2 ADSTB[0]# F26 D[13]# D[45]# Y22
B1 H_D#14 K22 AC26 H_D#46
7 H_REQ#[0..4] H_REQ#0 RESET# H_RS#0 H_CPURST# 7 D[14]# D[46]#
K3 F3 H_D#15 H25 AA24 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 7 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 H_RS#1 7 7 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 7
H_REQ#2 K2 G3 H_RS#2 G22 Y25
H_REQ#3 REQ[2]# RS[2]# H_RS#2 7 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
J3 REQ[3]# TRDY# G2 H_TRDY# 7 7 H_DINV#0 J26 DINV[0]# DINV[2]# V23 H_DINV#2 7
H_REQ#4 L5
7 H_A#[17..31] REQ[4]#
HIT# G6 H_HIT# 7
H_A#17 Y2 E4 H_D#16 N22 AC22 H_D#48
A[17]# HITM# H_HITM# 7 D[16]# D[48]#
H_A#18 U5 H_D#17 K25 AC23 H_D#49
H_A#19 A[18]# T450 H_D#18 D[17]# D[49]# H_D#50
R3 A[19]# ADDR GROUP 1 BPM[0]# AD4 1 P26 D[18]# D[50]# AB22
H_A#20 W6 AD3 1 T451 H_D#19 R23 AA21 H_D#51
A[20]# BPM[1]# D[19]# D[51]#
XDP/ITP SIGNALS
H_A#21 U4 AD1 1 T452 +VCCP H_D#20 L25 AB21 H_D#52
A[21]# BPM[2]# D[20]# D[52]#
DATA GRP 1
DATA GRP 3
H_A#22 Y5 AC4 1 T453 H_D#21 L22 AC25 H_D#53
H_A#23 A[22]# BPM[3]# T454 H_D#22 D[21]# D[53]# H_D#54
U2 A[23]# PRDY# AC2 1 L23 D[22]# D[54]# AD20
H_A#24 R4 AC1 1 T455 H_D#23 M23 AE22 H_D#55
H_A#25 A[24]# PREQ# TCK R34 56Ohm H_D#24 D[23]# D[55]# H_D#56
T5 A[25]# TCK AC5 P25 D[24]# D[56]# AF23
H_A#26 T3 AA6 TDI R4 56Ohm H_D#25 P22 AD24 H_D#57
H_A#27 A[26]# TDI TDO T456 H_D#26 D[25]# D[57]# H_D#58
W3 A[27]# TDO AB3 1 P23 D[26]# D[58]# AE21
H_A#28 W5 AB5 TMS R33 56Ohm H_D#27 T24 AD21 H_D#59
H_A#29 A[28]# TMS TRST# R6 56Ohm +VCCP H_D#28 D[27]# D[59]# H_D#60
Y4 A[29]# TRST# AB6 R24 D[28]# D[60]# AE25
H_A#30 W2 C20 1 T2 GND H_D#29 L26 AF25 H_D#61
H_A#31 A[30]# DBR# H_D#30 D[29]# D[61]# H_D#62
Y1 A[31]# T25 D[30]# D[62]# AF22
2
C V4 D21 H_PROCHOT_S# H_D#31 N24 AF26 H_D#63 C
7 H_ADSTB#1 ADSTB[1]# PROCHOT# R7 D[31]# D[63]#
THERMDA A24 THERMDA 6 7 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 7
THERM
24 H_A20M# A6 A20M# THERMDC A25 THERMDC 6 1KOhm 7 H_DSTBP#1 N25 DSTBP[1]# DSTBP[3]# AE24 H_DSTBP#3 7
24 H_FERR# A5 FERR# 7 H_DINV#1 M26 DINV[1]# DINV[3]# AC20 H_DINV#3 7
24 H_IGNNE# C4 IGNNE# THERMTRIP# C7 H_THRMTRIP# 6,24
GTLREF H_COMP0 R8 27.4Ohm
1
AD26 GTLREF COMP[0] R26 1 2
D5 MISC U26 H_COMP1 R9 1 2 54.9Ohm GND
24 H_STPCLK# STPCLK# COMP[1]
R11 H_COMP2 R10 27.4Ohm
HCLK
24 H_INTR C6 LINT0 COMP[2] U1 1 2
24 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 13 1 2 1KOhm C26 TEST1 COMP[3] V1 H_COMP3 R12 1 2 54.9Ohm
A3 A21 /*
24 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 13
2
1 R13 2 51Ohm D25 TEST2 DPRSTP# E5 H_DPRSTP# 24,47
1
AA1 C1 R14 GND B5
RSVD[1] DPSLP# H_DPSLP# 24
AA4 T22 0.1UF/16V 2KOhm D24
RSVD[2] RSVD[12] CPU_BSEL0 B22 DPWR# H_PWRGD H_DPWR# 7
AB2 RSVD[3] RSVD[A2] A2 /* 13 CPU_BSEL0 BSEL[0] PWRGOOD D6 H_PWRGD 24
CPU_BSEL1 B23 T3
2
AA3 RSVD[4] 13 CPU_BSEL1 BSEL[1] SLP# D7 1
CPU_BSEL2 C21
1
RESERVED
M4 RSVD[5] RSVD[13] D2 GND GND 13 CPU_BSEL2 BSEL[2] PSI# AE6 H_CPUSLP# 7,24
N5 RSVD[6] RSVD[14] F6 PM_PSI# 47
T2 RSVD[7] RSVD[15] D3 SOCKET_479P
V3 RSVD[8] RSVD[16] C1
B2 RSVD[9] RSVD[17] AF1
C3 RSVD[10] RSVD[18] D22
RSVD[19] C23
B25 RSVD[11] RSVD[20] C24
SOCKET_479P
B B
+VCCP +VCCP