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A B C D E
MYALL Block Diagram (Ref. rename from 12/6)
CLK GEN. Mobile CPU G792 Project Code: 91.4G501.001
4
19 4
IDT CV125 Dothan PCB: 05244-Rev.
3 4, 5
RGB CRT CPU DC/DC
HOST BUS 400MHz 14
ISL6218CV-T
34
DDR II 400MHz
Intel 910GM (UMA) INPUTS OUTPUTS
400 MHz LVDS LCD
11,12 Intel 915PM (DIS) VCC_CORE
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13 DCBATOUT
0.844~1.3V
DDR II 400MHz Nvidia VRAMx4 27A
400 MHz 6,7,8,9,10 G72M-V 24,25
11,12 24,25 SYSTEM DC/DC
3 DMI I/F 100MHz TPS51120 35 3
Line In27
INPUTS OUTPUTS
Mic In Azalia ENE DCBATOUT 3D3V_S5
27 Codec PCI BUS CB1410 PWR SW 5V_S5
PCMCIA APL5912-LAC
ALC861 CP2211
Int. 26 25 APL5308-25AC 36
24,25
ONE SLOT
MIC In 27 25 INPUTS OUTPUTS
5V_S5 1D5V_S0
Line Out 3D3V_S0 2D5V_S0
27
Mini-PCI SYSTEM DC/DC
OP AMP ICH6-M 802.11A/B/G 28
ISL6227 37
INT.SPKR G1421B 27 LAN INPUTS OUTPUTS
27
10/100
RTL8110CL
TXFM RJ4523 5V_S5
23 DCBATOUT
2 22, 23 3D3V_S3 2
MODEM PCIE X1 TPS51100DGQ 37
MDC Card PCI MINI CARD DDR_VREF
25 5V_S5
21 DDR_VREF_S3
LPC BUS
SATA CHARGER
ISL6255
15,16,17,18 38
USB Golden Xbus BIOS ROM
INPUTS OUTPUTS
PATA Finger KBC 512 K
30 ENE KB3910 PM39LV040-70JCE
PCB Layer Stackup USB 29 31 DCBATOUT
BT+
16.8V 3A
L1: Signal 1 SATA 5 PORT
24,25 HDD CDROM 21
L2:VCC 20 20
1 1
L3: Signal 2 Wistron Corporation dd
SATA MINI USB 21
Touch INT_KB Digitally signed by
L4: Signal 3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
BlueTooth Pad 30 DN: cn=dd, o=dd, ou
Taipei Hsien 221, Taiwan, R.O.C.
L5: GND 30
LED BDx1 BLOCK DIAGRAM email=dddd@yahoo.
Title
24,25
L6: Signal 4 Size Document Number c=US Rev
(co-lay) (another circuit) Custom
MYALL Date: 2009.11.29 07:5 SA
Date: Friday, February 10, 2006 Sheet 1 of 52
A B C D E
+07'00'
A B C D E
Alviso Strapping Signals ICH6-M Integrated Pull-up
and Configuration page 7 and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Pin Name Strap Description Configuration
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
CFG[2:0] FSB Frequency Select 000 = Reserved
001 = FSB533 EE_DOUT, GNT[5]#/GPO[17],
010 = FSB800 ICH6 internal 20K pull-ups
011-111 = Reversed GNT[6]#/GPO[16], LDRQ[1]/GPI[41],
4 CFG[3:4] Reversed LAD[3:0]#/FB[3:0]#, LDRQ[0],
4
CFG5 DMI x2 Select 0 = DMI x2 PME#, PWRBTN#, TP[3]
1 = DMI x4 (Default)
0 = DDR II
CFG6 DDR I / DDR II 1 = DDR I LAN_RXD[2:0] ICH6 internal 10K pull-ups
CFG7 CPU Strap 0 = Prescott
1 = Dothan (Default) ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
CFG[8:11] Reversed ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
CFG[12:13] XOR/ALL Z test 00 = Reserved SPKR, EE_CS,
straps 01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation USB[7:0][P,N] ICH6 internal 15K pull-downs
(Default)
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CFG[14:15] Reversed DD[7], SDDREQ ICH6 internal 11.5K pull-downs
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled LAN_CLK ICH6 internal 100K pull-downs
(Default)
CFG17 Reversed
CFG18 CPU core VCC 0 = 1.05V (Default)
Select 1 = 1.5V
3 CFG19 CPU VTT Select 0 = 1.05V (Default)
ICH6-M IDE Integrated Series 3
1 = 1.2V
CFG20 Reversed
PCI Routing Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
SDVOCRTL SDVO Present 0 = No SDVO device present IDSEL IRQ REQ/GNT approximately 33 ohm
_DATA (Default) DDACK#, IORDY, DA[2:0], DCS1#,
1= SDVO device present
1410 25 B.F.G 0 DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
MiniPCI 21 F 1
LAN 23 E 2
2 2
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Memo
Size Document Number Rev
A3
MYALL SA
Date: Friday, February 10, 2006 Sheet 2 of 52
3D3V_S0 3D3V_S0 3D3V_S0
1 R408 2 3D3V_APWR_S0 1 R444 2 3D3V_48MPWR_S0 1 R411 2 3D3V_CLKGEN_S0
0R0603-PAD 2R3J-2-GP 0R0603-PAD
1
1
1
1
1
1
1
1
C557 C580 C574 C556 C555 C558
C565 C591
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
IN EN OUT
(3D3V_S0) (6218_PGOOD) (VTT_PWRGD#)
H L H
? CHECK
X H Hi - Z 2 3 DREFSSCLK 7
31 PCLK_FWH 1 R436 2 33R2J-2-GP 1 4 DREFSSCLK# 7
SRN33J-5-GP-U
RN74
MYALL SC DREFSSCLK1 2 3 CLK_PCIE_MINI1 25
1D05V_S0 R400 1 U58
28 PCLK_MINI 2 33R2J-2-GP <2nd> DREFSSCLK#1 1 4 CLK_PCIE_MINI1# 25
RN75 SRN33J-5-GP-U
PCLK_MINI_1 56 17 CLK_PCIE_MINI1_1 RN76
PCI0 LVDS
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8 1 PCLK_KBC_1 3 18 CLK_PCIE_MINI1_1# 2 3 CLK_PCIE_PEG 42
29 PCLK_KBC PCI1 LVDS#
1
1
7 2 PCLK_PCM_1 4 1 4 CLK_PCIE_PEG# 42
24 PCLK_PCM PCLK_LAN_1 PCI2 SRN33J-5-GP-U
R438
DY
R401 22 PCLK_LAN 6 3 5 PCI3 SRC1 19
RN77
MYALL SB 16 CLK_ICHPCI 5 4 H/L: 100/96MHz SRC1# 20
1KR2J-1-GP 1KR2J-1-GP SS_SEL 9 22 2 3 CLK_PCIE_SATA 15
RN79 ITP_EN PCIF1/SEL100/96# SRC2
8 23 1 4 CLK_PCIE_SATA# 15
2
2
FS_A SRN33J-4-GP PCIF0/ITP_EN SRC2# CLK_SRCT3 SRN33J-5-GP-U
H/L : CPU_ITP/SRC7 SRC3 24
55 25 CLK_SRCN3
16 PM_STPPCI# PCI_STOP# SRC3# CLK_SRCT4 RN72
CPU_SEL1 7 SRC4 26 1 4 SRN33J-5-GP-U CLK_PCIE_ICH 16
CPU_SEL0 4,7 27 CLK_SRCN4 2 3 CLK_PCIE_ICH# 16
SRC4# CLK_PCIE_ICH1
11,18 SMBC_ICH 46 SCL SRC5 31
1
47 30 CLK_PCIE_ICH#1
11,18 SMBD_ICH SDA SRC5#
R427 33 CLK_MCH_3GPLL1 RN71 1 4 SRN47J-7-GP CLK_MCH_3GPLL 7
1KR2J-1-GP RN73 SRN33J-5-GP-U SRC6 CLK_MCH_3GPLL#1
SRC6# 32 2 3 CLK_MCH_3GPLL# 7
3 2 DREFCLK_1 14
7 DREFCLK DREFCLK#_1 DOT96
4 1 15 36
2
SC22P50V2JN-4GP 7 DREFCLK# DOT96# CPU2_ITP/SRC7
CPU2_ITP#/SRC7# 35
C571 XTAL_IN 50 44 CLK_CPU_BCLK1 RN69 1 4 SRN33J-5-GP-U CLK_CPU_BCLK 4
XTAL_OUT XTAL_IN CPU0 CLK_CPU_BCLK#1
1 2 49 XTAL_OUT CPU0# 43 2 3 CLK_CPU_BCLK# 4
41 CLK_MCH_BCLK1
2 CPU1
16 CLK_ICH14 1 2 33R2J-2-GP CPU1# 40 CLK_MCH_BCLK#1 RN70 1 4 SRN33J-5-GP-U CLK_MCH_BCLK 6
R520 52 2 3 CLK_MCH_BCLK# 6
X4 REF
SC MYALL 1 2 39 IREF CPU_STOP# 54 PM_STPCPU# 16,34
X-14D31818M-31GP R402 475R2F-L1-GP 53 CPU_SEL0
1
FSC/TEST_SEL CPU_SEL1
1 2 FSB/TEST_MODE 16
VTT_PWRGD# 10 12 FS_A 2 R437
1
CPU C568 VTT_PWRGD#/PD USB48/FSA 22R2J-2-GP CLK48_ICH 16
FS_C FS_B FS_A CLK_ICH14 & CLK14_SIO
SC27P50V2JN-2-GP
0 0 0 266M need equal length 2 34 3D3V_CLKGEN_S0
0 0 1 133M VSS_PCI VDD_SRC
6 21 RN82
0 1 0 200M VSS_PCI VDD_SRC CLK_PCIE_MINI1# 1 4
0 1 1 166M 51 7 CLK_PCIE_MINI1 2 3
1 0 0 333M VSS_REF VDD_PCI SRN49D9F-GP
45 VSS_CPU VDD_PCI 1
1 0 1 100M 38
1 1 0 400M VSSA
13 48 RN84
1 1 1 Reserved VSS48 VDD_REF CLK_PCIE_SATA#
29 VSS_SRC VDD_CPU 42 1 4
37 3D3V_APWR_S0 CLK_PCIE_SATA 2 3
VDDA 3D3V_48MPWR_S0
VDD48 11
28 SRN49D9F-GP
3D3V_S0 VDD_SRC
RN83
CLK_PCIE_PEG# 1 4
IDTCV125PAG-GP CLK_PCIE_PEG 2 3
SRN49D9F-GP
8
7
6
5
RN78
SB
SRN10KJ-4-GP CLK_CPU_BCLK RN66 1 4 SRN49D9F-GP
CLK_CPU_BCLK# 2 3
1
2
3
4