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A B C D E
FILE LIST 01
01_BLOCK DIAGRAM
LED CLOCK 02_REVISION LIST
CARMEL
THERMAL BOARD GEN 03_CPU_BANIAS(HOST)
1
04_CPU_BANIAS(PWR) 1
05
05_THERMAL
34 31
06_NB_MCHM(DDR)
07_NB_MCHM(HOST)
08_NB_MCHM(VGA)
BANIAS POWER POWER 09_NB_MCHM(PWR)
FAN (IMVP4) ON/OFF
Block Diagram CKTS
10_DDR SODIMM-0
11_DDR SODIMM-1
12_DDR_TERMINATION
32 03 04 35 41 33 13_LVDS & BACKLIGHT
PSB 14_CRT_CONNECTOR
2 15_ICH4-M(HUB_PCI) 2
LVDS DDR TERMINATION 16_ICH4-M(H_U_IDE_PM)
26 13 LCD MCHM 17_ICH4-M(PWR)
12 18_ICH4-M_PULLUP
RGB MONTARA 19_IDE_HDD
14 CRT -GM 20_IDE_CDROM
DDR DDR DDR
IO BOARD DIMM 0 DIMM 1
21_SUPER_I/O_87393
22_IR & LPT_PORT
23_LPC_KBC & PS2
10 11 24_DISCHARGE, DEBUG PORT
06 07 08 09
25_MDC
DC-DC 25 HUB
MODEM 26_IOBOARD
JACK 27_MINIPCI
3
AC LINK 3
MDC 28_RICOH551
ICH4 29_CB_PWR_551
FWH LAN PHY IDE PRIMARY SECONDARY 30_PCM_CONN(SIGNAL)
IDE IDE 31_CLOCK_ICS950811
32_FAN
15 16 17 18 33_PWR & RESET_SEQ
USB 19 20
MIC 34_LED BOARD
PORT
LPC DEBUG
OP AC97 PORT
4 4
1394 24
SOCKET CARDBUS
PORTBAR CON 30
PCI KBC SIO
IR
28 REV. LIST 02
LAN
PS2 CON 23 21 22
POWER MINIPCI
SWITCH
PRINTER USB PRINTER
PORT PORT 29 PORT
5 5
27
22
60-N4LMB1000-A01P
PROJECT:
A
WB REVISION DATE:
SHEET
B
Monday, January 13, 2003
1 OF
DESCRIPTION:
C
BLOCK DIAGRAM
SCHEMATIC FILE NAME :
LIBRARY DATE :
D
DESIGN ENGINEER :
E
A B C D E
PCB STACK-UP POWER INTERFACE
REVISION LIST PCB THICKNESS: 1.2 mm SIGNALS TYPE POWER
R1.0 2002/09/02 Initial CLK_EN# I +V3.3
L1 TOP
R1.1 2002/12/07 1) Pull ACIN_OC(R531) high to +V3.3 PM_PSI# O +VCCP
L2 GND1
1
2) Pull BAT1_IN#_OC(R532) high to +V3.3 VR_VID[5:0] O +VCCP 1
L3 IN1
3) Pull BAT2_IN#_OC(R533) high to +V3.3 1.5V_PWRGD I +V3.3
L4 IN2
4) Change Q90 to U57(same P/N:06-004600000) 1.8V_PWRGD I +V3.3
L5 VCC
5) U46 Pin6 connected to +V3.3SUS CPU_VRON O +V3.3
L6 IN3
R1.2 2002/12/27 VRM_PWRGD I +V3.3
L7 GND2
PM_STPCPU# O +V3.3
L8 BOT
CHG_LED I +V3.3
IMPEDENCE RST_BTN# O +V3.3
Single-Ended OTP_RESET# I +V3.3
SHUT_DOWN# I +V3.3
27.4 OHM WID H T
+V5_LCM PWR +V5
TOP/BOT 22 mils
2 IN1/IN3 16 mils PM_SLPDLY_S3# O +V3.3 2
PM_SLP_S4# O +V3.3
37.5 OHM WID HT
BAT_LEARN I +V3.3
TOP/BOT 13.5 mils
IN1/IN3 10 mils BAT_LLOW#_OC I +V3.3
BAT1_IN#_OC I +V3.3
42 OHM WID HT
BAT2_IN#_OC I +V3.3
TOP/BOT 11 mils
IN1/IN3 8.5 mils ACIN_OC I +V3.3
CHG_EN_OC I +V3.3
55 OHM WID H T
PM_DPRSLPVR O +V3.3
TOP/BOT 6 mils
IN1/IN3 5 mils ACIN_3VA I +V3.3
+5VAO PWR +V3.3
75 OHM WID H T
EN_+3VALWAYS O +V3.3
TOP/BOT 2.5 mils
3
IN1/IN3 2 mils AC_BAT_SYS PWR DC 3
A/D_DOCK_IN PWR DC
Differential
SMC_BAT1 IO +V3.3
70 OHM WIDTH/SPACE
SMD_BAT1 IO +V3.3
TOP/BOT 8 mils/ 4 mils
IN1/IN3 8 mils/ 3.5 mils SMC_BAT2 IO +V3.3
SMD_BAT2 IO +V3.3
90 OHM WIDTH/SPACE
BAT_LOW# I +V5_LCM
TOP/BOT 5 mils/ 5 mils
IN1/IN3 5 mils/ 5 mils POWER PLANE
100 OHM WIDTH/SPACE POWER VOLTAGE CURRENT
TOP/BOT 4 mils/ 6 mils +VCORE 1.46V 25A
IN1/IN3 4.25 mils/ 5.75 mils +VCCP 1.05V 2.5A
4 4
+V1.2S 1.2V 2.5A
PCI INTERFACE +V1.25S
+V1.5S
1.25V
1.5V
0.5A
1.32A
PCI_REQ#
+V1.5 1.5V 30 mA
CB&1394 PCI_REQ#0 +V1.5SUS 1.5V 64 mA
MINIPCI PCI_REQ#1 +V1.8S 1.8V 0.3 A
+V2.5 2.5V 6.68A
IDSEL
+V3.3S 3.3V 1.732A
MINIPCI PCI_AD20 +V3.3 3.3V 1.515A
CB&1394 PCI_AD21 +V3.3SUS 3.3V 14 mA
+V5S 5V 2.5A
5
+V5 5V 3.75A 5
+V5SUS 5V 0.5A
+V12 12V 0.25A
+V12S 12V 0.25A
REVISION DATE: Monday, January 13, 2003 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: WB SHEET 2 OF
REVISION LIST LIBRARY DATE :
A B C D E
A B C D E
CPU Pin A1 need to be enlarged(M) H_D#[63:0] 7
U27B U27A
7 H_A#[16:3] H_A#16 AA2 N2 COMMON CLOCK -> L6 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# 7 D[15]# D[47]#
H_A#15 Y3 A10 H_PRDY# H_D#14 E23 AA26 H_D#46
A[15]# PRDY# WIDTH: 4 mils D[14]# D[46]#
H_A#14 AA3 B10 H_PREQ# H_D#13 B23 Y23 H_D#45
H_A#13 U1 A[14]# PREQ# SPACE >= 1:2 H_D#12 C26 D[13]# D[45]# V26 H_D#44 DATA GROUP 0,2 -> L3
H_A#12 Y1 A[13]# L1 GROUP SPACE>=1:5 H_D#11 E24 D[12]# D[44]# U25 H_D#43
H_A#11 Y4 A[12]# BNR# J3 H_BNR# 7 H_D#10 D24 D[11]# D[43]# V24 H_D#42 DATA GROUP 1,3 -> L6
1 A[11]# BPRI# H_BPRI# 7 LENGTH: 1" - 6.5"(OPT: 4"+/-0.5") D[10]# D[42]# 1
H_A#10 H_D#9 H_D#41 SPACE >= 1 :3
ADDRESS GROUP 0
W2 B24 U26
DATA GROUP 0
Breakout Length:<=200 mil
DATA GROUP 2
H_A#9 T4 A[10]# H_D#8 C20 D[9]# D[41]# AA23 H_D#40
H_A#8 W1 A[9]# A7 1 T3 TPC28 (#0011) H_D#7 B20 D[8]# D[40]# R23 H_D#39 GROUP SPACE >=1:5
H_A#7 V2 A[8]# DBR# H_D#6 A21 D[7]# D[39]# R26 H_D#38
H_A#6 R3 A[7]# H_D#5 B26 D[6]# D[38]# R24 H_D#37 LENGTH: 0.5" - 5.5"
A[6]# D[5]# D[37]#
H_A#5 V3
A[5]#
H_D#4 A24
D[4]# D[36]#
V23 H_D#36 (#0012)
H_A#4 U4 L4 H_D#3 B21 U23 H_D#35
A[4]# DEFER# H_DEFER# 7 D[3]# D[35]#
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# 7 D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
7 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 7 D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 D25 T24
REQ[3]# 7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7
H_REQ#2 T2 C23 W25
REQ[2]# 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#1 P3 C22 W24
REQ[1]# 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#0 R2
REQ[0]# N4 H_BR0# H_D#31 K25 AF26 H_D#63
7 H_REQ#[4:0] BR0# H_BR0# 7 D[31]# D[63]#
CONTROL
+VCCP H_D#30 N25 AF22 H_D#62
H_D#29 H26 D[30]# D[62]# AF25 H_D#61
A4 H_IERR# R217 1 2 56 H_D#28 M25 D[29]# D[61]# AD21 H_D#60
IERR# H_D#27 N24 D[28]# D[60]# AE21 H_D#59
7 H_A#[31:17] 0.5"-12" D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
H_A#30 A[31]# H_D#25 D[26]# D[58]# H_D#57
<=10"
DATA GROUP 3
AE1 B5 J25 AD24
DATA GROUP 1
A[30]# INIT# H_INIT# 16,26 D[25]# D[57]#
H_A#29 AF3 H_D#24 M23 AF23 H_D#56
H_A#28 AD6 A[29]# H_D#23 J23 D[24]# D[56]# AE22 H_D#55
2 ADDR GROUP 0 ->L3 A[28]# D[23]# D[55]# 2
H_A#27 AE2 J2 <=10" H_D#22 G24 AD23 H_D#54
ADDRESS GROUP 1
ADDR GROUP 1 ->L6 H_A#26 AD5 A[27]# LOCK# H_LOCK# 7 H_D#21 F25 D[22]# D[54]# AC25 H_D#53
SPACE >= 1:2 H_A#25 A[26]# H_D#20 D[21]# D[53]# H_D#52
AC6 H24 AC22
STROBE SPACE >=1:3 H_A#24 AB4 A[25]# H_D#19 M26 D[20]# D[52]# AC20 H_D#51
H_A#23 AD2 A[24]# H_D#18 L23 D[19]# D[51]# AB24 H_D#50
GROUP SPACE>=1:5 A[23]# D[18]# D[50]#
H_A#22 AE4 H_D#17 G25 AC23 H_D#49
H_A#21 AD3 A[22]# B11 H_D#16 H23 D[17]# D[49]# AB25 H_D#48
<=3"
LENGTH: 0.5" - 6.5" H_A#20 AC3 A[21]# RESET# L2 H_RS#2 H_CPURST# 7
J26 D[16]# D[48]# AD20
7 H_DINV#1 H_DINV#3 7
(#0012) H_A#19 AC7 A[20]#
A[19]#
RS[2]#
RS[1]#
K1 H_RS#1 7 H_DSTBN#1 K24 DINV[1]#
DSTBN[1]#
DINV[3]#
DSTBN[3]#
AE24 H_DSTBN#3 7
H_A#18 AC4 H1 H_RS#0 L24 AE25
A[18]# RS[0]# 7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7
H_A#17 AF4
A[17]# H_RS#[2:0] 7
AE5 M3 SOCKET479P
7 H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# 7
K3
HIT# H_HIT# 7
K4
HITM# H_HITM# 7 +VCCP +VCCP
SOCKET479P TOPOLOGY 2A: TOPOLOGY 1B:
R-CPU-ICH Y-FORK CPU-ICH-R
2
2
H_VID5 VR_VID5 35
H_VID4 VR_VID4 35 CPU-ICH: 0.5" - 12" R23 CPU-ICH: 0.5" - 12" R404
H_VID3 332 56 +VCCP
H_VID2 VR_VID3 35 R - CPU <= 3" ICH-R <= 3"
3 8 H_DPWR# 1"-6.5" C19 VR_VID2 35 Close to 3
DPWR# H_VID1 (#0013) (#0013)
VR_VID1 35 Pin AD26
2
H_VID0 H_PWRGD H_FERR#
1