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1 2 3 4 5 6 7 8
INT@:UMA
EXT@:Discrete
V6@:64M VRAM
V12@:128M VRAM
G5@:LAN 5705E
G7@:LAN 5787
ZE2 DC/DC
REV:A1A
AC/BATT NVDD/+1.2V CPU VR CLOCKS Generator
A
G9@:LAN 5709 A
CONNECTOR Page 41 Yonah/Celeron-M +3V/+5V SC452 ICS954310BGLF
+1.05V/+1.8VSUS/+1.8V/+0.9V
+1.5V/+2.5V Page 35,37,38,39 Page 36 Page 3
(479 Micro-FCPGA)
BATT Page 4,5
CHARGER Page 40
+0.9V EXT. VGA EXT_LVDS SWITCH LCD Connector
+0.9VSUS Page 28
+1.8VSUS HOST BUS 533/667 MHz n-VIDIA NV72MV
EXT_TVOUT
DDR-SODIMM1 DDR2 533/667 MHz +1.05V Page 12,13,14,15
Page 10,11
EXT_VGA
INT_LVDS
DDR2 533/667 MHz CALISTOGA-GM/PM CIRCUIT VGA CRT
B
DDR-SODIMM2 INT_TVOUT Page 17 B
Page 10,11 +1.5V
1466 FCBGA
INT_VGA Page 17
+1.8VSUS
+2.5V
Page 6,7,8,9 DVI
CH7307 DOCKING EZ4 DVI
Page 33
Parallel-HDD ATA 66/100 Page 16
Page 32
DMI interface
MINI card
Page 29
ATA 66/100 +1.5V +1.05V
Multi-Bay
Page 32 +2.5V LAN (10M/100M/1G)
ICH7-M PCIe
Azalia +3V BCM5787M/5789M
652 BGA Page 23
+3VSUS RJ45
C C
+1.5VSUS Page 24
33MHz PCI
Page 18,19,20 LAN (10M/100M/1G)
ALC833 BCM 5705E Page 23
MDC1.5 AD22 / REQ1# / GNT1# /INTA#
(Codec)
& 2 AMP Page 30
Page 30 CARDBUS/1394/3-IN-1 1394 PORT
RJ11 TI 7411 Page 21
Page 21,22
Page 24 AD25 / REQ0# / GNT0# /INT E/F/G#
Head phone
Page 31
USB
USB PORT X 3
INT SPK Page 25
Page 31 SUPER I/O 3V_591
3 in 1 CARDBUS
Internal-MIC PC87391 EC NSC97551 Mini-Bluetooth socket CON.
Page 31 Page 26 (USB bus) MMC,SD,MS Page 22
D 176 Pins LQFP Page 27 D
MIC-IN Page 25
Page 31 Page 22
COM A COM B
PROJECT : ZE2
LINE-IN +5V +5V +3VPCU +5V Finger
Page 31 Digitizer FIR Printer Page 28 Quanta Computer Inc.
Size Document Number Rev
JOGDIAL Keyboard FLASH FAN 1 Schematic Block Diagram E2C
Page 26 Page 26 Page 28 Page 27 Page 27 Page 25 Date: Thursday, June 08, 2006 Sheet 1 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
5/5 page29 MINI CARD pin define changed for debug card
5/8 page31 Audio Jack GND connect to DGND
5/10 page09 modify GMCH power for G72MV(original some parts no stuff for descrete,modify to stuff)
5/10 page37,38 change PQ36,PQ37,PQ38,PQ40,PQ41,PQ45,PQ53 part number to BAM64020009 for EOL issue
5/10 page31 change D19,D20,D22 part number to BC1SS355Z05 for EOL issue
6/4 page26,27 change S_SERIRQ net name to SERIRQ for fix KB no function issue, and add a cap of SERIRQ if noise
6/4 page30 ,stuff U53 ,no stuff L60 for audio noise
6/4 page31 R633 change from 15K to 22K to fix speaker voice is too low issue
6/4 page31 tie SURR-L and SURR-R for fix no sound when volume bar adjust to right channel
6/4 page30 change R627,R629 from 0 ohm to 4.7K ohm for fix HP voice is too loud
6/4 page31 change R635,R640 change from 0 to 75 ohm for fix noise by ZC3 solution
A
6/4 page31 add cap on linein_PR for fix audio noise from docking Line in A
6/4 page28 LCD connector pin34 change to +3V for fix EDID LCD issue
6/4 page13 add LCDID to VGA for Toshiba LCD that is no EDID support issue
6/4 page19 change USB I/O port from port1 to port2 for Bluetooth detection issue
6/4 page13 stuff R496 for fix no CRT issue by VGA SKU
6/4 page27 change 1M BIOS ROM from B-stage
6/4 page35 change PR55,PR146 to 100K and PC44,PC141 to 0.1uF to meet Nvidia power sequence requirement
6/4 page32 add ODD RST PU resistor for S/W not ready
6/4 page38 PL22 chagne p/n to CV-33D5MZ04 for package and footprint are difference issue
6/4 page42 add modem hole for modem NUT issue
6/4 page31 R630 change to LF part
6/4 page36 change PC15,PC16,PR16,PR18 value for power requirement
6/4 page35 change PR150 from 20K to 24K value for power requirement
6/4 page36 Add snubber of 2.2 ohm/2200pf on CPU core
6/4 page35,38,39 del short PAD
6/4 page28 un stuff CN3 PCI debug card
6/4 page15 R452,R478 change from 1K to 1.3K,R453,R469 change from 1K to 510 ohm ,Vref change from 0.5VDDQ to 0.7VDDQ for VRAM CLK un-stable issue
6/4 page14 R462, change from 1K to 1.3K,R461 change from 1K to 510 ohm ,Vref change from 0.5VDDQ to 0.7VDDQ for VRAM CLK un-stable issue
6/4 page42 change DIM H26,H35,H37 for SMT A open issue
6/7 page19 stuff R340 for PCI LAN wake up
6/7 page20,add RBAYID0,RBAYID1 PU for Swap Bay
6/8 page31,reserve 0 ohm resistor for EMI request
6/8 page19,change USB port for BT detection issue
6/9 page31 C836 change to 0.1uf for background noise
6/9 page40 change PD19 p/n for EOL issue
B B
C C
SKU MB ID BOM Property ASSY PN Description VRAM vender
A test SKU1 ZE2A 31ZE2MB0006 ZE2 M/B ASSY (GM/5705E)
A test SKU2 ZE2B 31ZE2MB0014 ZE2 M/B ASSY (PM/G72MV/64M/5787) Samsung 8M*32
A test SKU3 ZE2C 31ZE2MB0022 ZE2 M/B ASSY(PM/G72MV/128M/5789) Samsung 16M*32
B test SKU3 ZE2D 31ZE2MB0031 ZE2 M/B ASSY (GM)
D D
Size Document Number Rev
E2C
Date: Friday, June 09, 2006 Sheet 2 of 42
1 2 3 4 5 6 7 8
A B C D E
VDD_A
Close to IC <500mils
C409 27P-50V_4 CG_XIN
Place these termination to close CK410M.
45
46
2
L54 25 mils U20
BK2125HS121-T_8 Y2 58 60 14M_REF R543 33_4
VDDA
GNDA
X1 REF0 14M_ICH [20]
+3V VDD_SRC_CPU 14.318MHZ
C437 27P-50V_4 CG_XOUT 57 52 R_HCLK_CPU RP33 1 2 33_4P2R_S CLK_CPU_BCLK [4]
1
C401 C399 C440 C441 C756 X2 CPUCLKT0 R_HCLK_CPU# C742
120 ohms@100Mhz 51 3 4 CLK_CPU_BCLK# [4]
.1U-10V_4 10U-10V_8 R259 *10K_4 CPUCLKC0 *10P-50V_4
L:300mA +3V CK-410M
.1U-10V_4 .1U-10V_4 .1U-10V_4 [20,36] VR_PWRGD_CK410# 10 49 R_HCLK_MCH RP34 1 2 33_4P2R_S
Vtt_PwrGd#/PD CPUCLKT1 CLK_MCH_BCLK [6]
[20] PM_STPCPU# PM_STPCPU# 62 48 R_HCLK_MCH# 3 4
CPU_STOP# CPUCLKC1 CLK_MCH_BCLK# [6]
R540 2.2/F_6 VDD_A [20] PM_STPPCI# PM_STPPCI# 63 PCI/PCIE_STOP# R_CLK_PCIE_MINI1 RP35 1
CPUCLKT2/PCIET8 44 2 33_4P2R_S CLK_PCIE_MINI1 [29]
4 C400 C386 CGCLK_SMB R_CLK_PCIE_MINI1# 4
[10] CGCLK_SMB 54 SCLK CPUCLKC2/PCIEC8 43 3 4 CLK_PCIE_MINI1# [29]
.1U-10V_4 10U-10V_8 CGDAT_SMB 55
[10] CGDAT_SMB SDATA
41 R_CLK_PCIE_EZ2 RP36 1 2 33_4P2R_S
REQ1#/PCIET7 CLK_PCIE_EZ2 [33]
CLK_BSEL0 R547 4.7K_4 R_48M 12 40 R_CLK_PCIE_EZ2# 3 4
FSA/USB_48MHz REQ2#/PCIEC7 CLK_PCIE_EZ2# [33]
CLK_BSEL1 16
CLK_BSEL2 R220 4.7K_4 R_14M_SIO 61 FSB/TEST_MODE R_SRC_MCH RP37 1
REF1/FSLC/TEST_SEL PCIET6 39 2 33_4P2R_S CLK_PCIE_3GPLL [7]
38 R_SRC_MCH# 3 4
PCIEC6 CLK_PCIE_3GPLL# [7]
VDD_REF 56
VDD_SRC_CPU VDD_REF R_CLK_PCIE_EZ1 RP38 1
50 VDDCPU PCIET5 36 2 33_4P2R_S CLK_PCIE_EZ1 [33]
25 mils 35 R_CLK_PCIE_EZ1# 3 4
PCIEC5 CLK_PCIE_EZ1# [33]
VDD_PCI 1
L28 VDD_PCI VDD_PCI_1 R_CLK_PCIE_VGA RP41 3
+3V 7 VDD_PCI_2 PCIET4 30 4 EXT@33_4P2R_S CLK_PCIE_VGA [12]
BK2125HS121-T_8 31 R_CLK_PCIE_VGA# 1 2
PCIEC4 CLK_PCIE_VGA# [12]
L:300mA C442 C443 C451 VDD_SRC_CPU 21 VDD_PCIE
28 VDDPCIE SATA_CKT 26
.1U-10V_4 .1U-10V_4 10U-10V_8 42 27
VDD_PCIE SATA_CKC
VDD_48 11 24 R_SRC_ICH RP40 3 4 33_4P2R_S
VDD_48 PCIET3 CLK_PCIE_ICH [19]
25 R_SRC_ICH# 1 2
PCIEC3 CLK_PCIE_ICH# [19]
CLKGN_REQ3_PCIE 32
CLKGN_REQ4_PCIE REQ3(PCIE) R_CLK_PCIE_LAN RP39 3 G7_G9@33_4P2R_S
[33] EZ_CLKREQ# 33 REQ4(PCIE) PCIET2 22 4 CLK_PCIE_LAN [23]
R263 2.2/F_6 VDD_48 23 R_CLK_PCIE_LAN# 1 2
PCIEC2 CLK_PCIE_LAN# [23]
R541 475/F_6 IREF 47
C444 C457 Iref=5mA, Ioh=4*Iref IREF
PCIET1 19
PCIEC1 20
.1U-10V_4 10U-10V_8
DREFCLK RP42 1 2 INT@33_4P2R_S R_DOT96 14 17 R_DREFSSCLK RP43
3 4 INT@33_4P2R_S
[7] DREFCLK DOT96MHz 27Mfix/LCD_SSCGT/PCIE0T DREFSSCLK [7]
DREFCLK# 3 4 R_DOT96# 15 18 R_DREFSSCLK# 1 2
[7] DREFCLK# DOT96MHz# 27SS/LCD_SSCGC/PCIE0C DREFSSCLK# [7]
5 R_PCLK_SIO R258 33_4
selPCIEX0_LCD#/PCI5 PCLK_SIO [26]
T51 34 4 R_PCLK_LAN R257 G5@33_4
GND_PCI_1
GND_PCI_2
PWRSAVE# PCI4 PCLK_LAN [23]
GND_SRC
3 R_PCLK_PCM R552 33_4
PCI3 PCLK_PCM [21]
GND_48
R218 1_6 VDD_REF INTERNAL PULL HIGH 64 R_PCLK_DEBUG R219 33_4
PCICLK2/REQ_SEL PCLK_DEBUG [28,29]
9 R_PCLK_ICH R553 33_4
GND
GND
GND
3 PCIF1/selLCD_27# PCLK_ICH [19] 3
C398 C389 8 R_PCLK_591 R551 33_4
PCIF0/ITP_EN PCLK_591 [27]
R558 33_4
.1U-10V_4 10U-10V_8 [20] CLKUSB_48 R548 22R R_48M ICS954310BGLF
[21] TI-48M
53
13
59
2
6
29
37
pin5,pin9,pin32,pin33,pin34 internal PU
R221 33_4 R_14M_SIO pin64 internal PD
[26] 14M_SIO
C392
*10P-50V_4
Terminal Resistor
PCIE CLK enable/disable control Starpping SEL2 SEL1 SEL0
Frequence select FSC FSB FSA CPU SRC PCI CLK_CPU_BCLK R208 49.9/F_4
R_PCLK_SIO R261 10K_4
+3V
1 0 1 100 100 33 CLK_CPU_BCLK# R209 49.9/F_4
Latched Select. (Pin 17,18) 0 0 1 133 100 33 Default
R265 10K_4 CLKGN_REQ3_PCIE "0" : LCD CLK CLK_MCH_BCLK R210 49.9/F_4
"1" : PCIEX CLK 0 1 1 166 100 33 CLK_MCH_BCLK# R211 49.9/F_4
REQ3 Latched Select
"0" : CLK Enable 0 1 0 200 100 33 CLK_PCIE_VGA RP46 3 4 [email protected]_4P2R_S
CLK_PCIE_VGA# 1 2
"1" : CLK Disable Control : PCIE 2,4
R_PCLK_591 R556 10K_4
0 0 0 266 100 33 CLK_PCIE_LAN RP44 3 4 [email protected]_4P2R_S
1 0 0 333 100 33 CLK_PCIE_LAN# 1 2
ITP/SRC7 SELECT
0: SRC7 1 1 0 400 100 33 CLK_PCIE_3GPLL RP31 1 2 49.9_4P2R_S
2 1: ITP CLK_PCIE_3GPLL# 3 4 2
1 1 1 200 100 33 CLK_PCIE_MINI1 RP29 1 2 49.9_4P2R_S
CLK_PCIE_MINI1# 3 4
BSEL strappings need to be set for 533MHz Moby Dick
R_PCLK_ICH R554 10K_4 (Intel?915GM - Calistoga Interposer) CLK_PCIE_ICH RP45 3 4 49.9_4P2R_S
+3V (if Calistoga is designed for 667MHz board).
+3V CLK_PCIE_ICH# 1 2
SELLCD_27# Select. (Pin 17,18)
R203 10K_4 CLKGN_REQ4_PCIE "0" : 27MHzSS/27MHzSS# pair DREFSSCLK RP48 3 4 [email protected]_4P2R_S
"1" : LCD CLK pair DREFSSCLK# 1 2
+1.05V R268 *1K_4
REQ4 Latched Select DREFCLK RP47 3 4 [email protected]_4P2R_S
"0" : CLK Enable DREFCLK# 1 2
R269 0_4 CLK_BSEL0 R270 1K_4 MCH_BSEL0 [7]
"1" : CLK Disable Control : PCIE 3,5,7 [4] CPU_BSEL0
CLK_PCIE_EZ2 RP30 1 2 49.9_4P2R_S
R_PCLK_DEBUG R262 *10K_4 R272 *1K_4 CLK_PCIE_EZ2# 3 4
+3V
PCIE CLK/REQ select CLK_PCIE_EZ1 RP32 1 2 49.9_4P2R_S
"0" : PCIE CLK CLK_PCIE_EZ1# 3 4
"1" : REQ pin
+1.05V R550 *1K_4
Reserve for EMI
SM BUS level shift R549 0_4 CLK_BSEL1 R545 1K_4 MCH_BSEL1 [7]
[4] CPU_BSEL1
PCLK_SIO C450 *10P-50V_4
+3V R557 *0_4
PCLK_LAN C449 *G5@10P-50V_4
PCLK_PCM C753 *10P-50V_4
R534 R535 PCLK_DEBUG C393 *10P-50V_4
Q34
2
1 RHU002N06 10K_4 10K_4 +1.05V R533 *1K_4 PCLK_ICH C754 *10P-50V_4 1
3 1 CGDAT_SMB PCLK_591 C752 *10P-50V_4
[20,23,29,33] PDAT_SMB
R532 0_4 CLK_BSEL2 R531 1K_4
[4] CPU_BSEL2 MCH_BSEL2 [7]
R542 *0_4
+3V
PROJECT : ZE2
Q35
2
RHU002N06 Power check Quanta Computer Inc.
3 1 CGCLK_SMB
[20,23,29,33] PCLK_SMB