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1 2 3 4 5 6 7 8
PCB STACK UP BL5S Block Diagram
LAYER 1 : TOP
LAYER 2 : SGND
Azalia
Intel
LAYER 3 : IN1 Transmitter CLOCK GENERATOR
HDMI Merom
A Page 20 Sil1392 CK505 A
LAYER 4 : IN2 Page 20 (35W) ICS9LPR363
Page 2
LAYER 5 : VCC Page 3,4
TV-OUT
LAYER 6 : BOT Page 22 FSB(667/800MHZ)
CRT
CRT SDVO
Page 18 Azalia
HDMI
VCC_CORE PCI-E X16 VGA CONNECTOR
R.G.B LCD
LCD(WXGA+ 15.4W) Crestline GM
Page 18 TV-OUT
Page 19
+1.5V LVDS X2
533/ 667 MHZ DDR II
SATA X2 Page 5,7,8,9,10,11
SATA - TWO HDD
Page 22
+1.05V DDRII-SODIMM1
PATA DDRII-SODIMM2
IDE - ODD DMI(x2/x4) Page 12,13
Page 22
B +1.25V B
USB CONN 1 PCI-Express
Page 19
+1.8VSUS
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USB CONN 2 MINI CARD MINI CARD MINI CARD NEW CARD Giga/100/10 LAN
Page 19
WLAN Marvell_8040
Page 25 Page 25 Page 25 Page 28 Page 24
8055
USB 2.0
+3VPCU USB CONN3 ICH8M
+3V_S5 Page 19
+3VSUS Azalia RJ45
+3V USB CONN 4
+5VPCU DAUGHTER BOARD Page 19
+5V_S5 PCI Bus
+5V WLAN Page 14,15,16,17
SMDDR_VTERM Page 25
SMDDR_VREF Card Port-A
Finger Printer LPC Reader/1394
32.768KHz AUDIO CODEC HP(SPDIF)
Page 28 OZ129T (CX20561) Page 27
Page 23
Port-B
C Bluetooth Page 26 C
INT SPK
Page 28 DIB_N DIB_P
SPK AMP Page 26
1394 Page 26
5 IN 1
New Card WPC8769LDG
WPCE775L MODEM CONN Port-C
INT MIC
Page 28 (CX20548) Page 18,27
Page 29
Felica Page 26
MIC JACK
Page 28 Page 27
Camera FAN Touch Key FLASH CIR
FM TUNER
Page 18 PAD Board ROM Page 27
USB X2 RJ11
Digitally signed by fdsf RJ11/USB DAUGHTER BOARD
DN: cn=fdsf, o=fsdfsd,
D ou=ffsdf, D
email=fdfsd@fsdff, c=US
Date: 2009.11.04 Quanta Computer Inc.
18:25:59 +07'00' Size
PROJECT : BL5S Santa Rosa
Document Number
Block Diagram
Rev
1A
Date: Tuesday, January 22, 2008 Sheet 1 of 37
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator
Clock Gen Differential IO +1.25V_VDD +1.25V
power
L22
+3V L21 PBY160808T-301Y-N_6 C291 0.1u/10V_4 PBY160808T-301Y-N_6
C281 C282 C257 C260 C297 C256 C296 C300
C270
C299 0.1u/10V_4 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
10u/10V_8 *10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
D C271 10u/10V_8 D
H=1.2mm ICS9LPRS365BGLFT
C253 0.1u/10V_4 U9 IC(64P) ICS9LPRS365BGLFT(TSSOP)
VDD_CK_VDD_48 2 48
C295 0.1u/10V_4 VDD_CK_VDD_48 VDD_PCI IO_VOUT
H=1.5mm VDD_CK_VDD_48
9
16
VDD_48
64 CGCLK_SMB
VDD_PLL3 SCLK CGCLK_SMB (13)
C272 27p_4 CG_XIN VDD_CK_VDD_48 61 63 CGDAT_SMB CGDAT_SMB (13)
VDD_REF SDA
CK505
2
Y2 C259 0.1u/10V_4 VDD_CK_VDD_48 39 38 PM_STPPCI# (16)
CL=20p VDD_CK_VDD_48 VDD_SRC SRC5/PCI_STOP#
55 VDD_CPU SRC5#/CPU_STOP# 37 PM_STPCPU# (16) To SB
14.318MHZ
+1.25V_VDD 12 54 CLK_CPU_BCLK_R RP32 1 2 0X2 CLK_CPU_BCLK (3)
1
C280 27p_4 CG_XOUT C255 0.1u/10V_4 VDD_96_IO CPU0 CLK_CPU_BCLK#_R
20 VDD_PLL3_IO CPU0# 53 3 4 CLK_CPU_BCLK# (3) To CPU
26 VDD_SRC_IO_1
45 51 CLK_MCH_BCLK_R RP33 1 2 0X2
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK (5)
36 50 CLK_MCH_BCLK#_R 3 4 To NB
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# (5)
10/26 REV_A1 Change Value 49 VDD_CPU_IO
47 CLK_PCIE_MINI3_R RP34 1 2 0X2
SRC8/ITP CLK_PCIE_MINI3 (25)
46 CLK_PCIE_MINI3#_R 3 4 To MINI3
SRC8#/ITP# CLK_PCIE_MINI3# (25)
R259 33_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP40 1 2 0X2
(25) PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# (6)
34 CLK_PCIE_3GPLL_R 3 4 To NB
SRC10 CLK_PCIE_3GPLL (6)
PCLK_PCM R264 33_4 PCLK_PCM_R 3
T49 PCI1/CR#_B
+3V R277 10K_4 33 CLK_MCH_OE#_R R237 475_4 CLK_MCH_OE# (6)
R265 33_4 PCLK_R5C833_R SRC11/CR#_H NEW_CLKREQ#_R R262 475_4
(23) PCLK_OZ129 4 PCI2/TME SRC11#/CR#_G 32 NEW_CLKREQ# (28)
R271 *10K_4
R266 10K_4 PCI_CLK_SIO_R 5 30 CLK_PCIE_NEW_R RP46 3 4 0X2
PCI3 SRC9 CLK_PCIE_NEW (28)
+3V R278 *10K_4 31 CLK_PCIE_NEW_R# 1 2 To New Card
SRC9# CLK_PCIE_NEW# (28)
R267 33_4 PCLK_591_R 6
(29) PCLK_591 PCI4/SRC5_EN
R272 10K_4 44 CLK_PCIE_MINI2_R RP35 1 2 0X2
C SRC7/CR#_F CLK_PCIE_MINI2 (25) C
R268 33_4 PCLK_ICH_R 7 43 CLK_PCIE_MINI2#_R 3 4 To MINI2
PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_MINI2# (25)
+3V R279 *10K_4
CG_XIN 60 41 CLK_PCIE_MINI_R RP36 1 2 0X2
(15) PCLK_ICH XTAL_IN SRC6 CLK_PCIE_MINI (25)
R273 10K_4 40 CLK_PCIE_MINI#_R 3 4 To WLAN
SRC6# CLK_PCIE_MINI# (25)
CG_XOUT 59 XTAL_OUT CLK_PCIE_LAN_R RP45
SRC4 27 3 4 0X2 CLK_PCIE_LAN (24)
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R274 33_4 FSA 10 28 CLK_PCIE_LAN#_R 1 2 To LAN
(16) CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_LAN# (24)
CLK_BSEL0 R275 2.2K_4
CLK_BSEL1 57 24 CLK_PCIE_ICH_R RP44 3 4 0X2
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH (15)
25 CLK_PCIE_ICH#_R 1 2 To SB
SRC3#/CR#_D CLK_PCIE_ICH# (15)
CLK_BSEL2 R231 10K_4 FSC 62 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP43
SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA (14)
R228 33_4 8 22 CLK_PCIE_SATA#_R 1 2 To SB
(16) 14M_ICH VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# (14)
11 VSS_48
15 17 DREFSSCLK_R
VSS_IO SRC1/SE1 DREFSSCLK#_R
19 VSS_PLL3 SRC1#/SE2 18
52 VSS_CPU
23 13 DREFCLK_R RP41 3 4 IV@0X2
VSS_SRC1 SRC0/DOT96 DREFCLK (6)
29 14 DREFCLK#_R 1 2 To NB
VSS_SRC2 SRC0#/DOT96# DREFCLK# (6)
42 VSS_SRC3
58 VSS_REF CKPWRGD/PWRDWN# 56 CK_PWRGD (16)
ICS9LPRS365AGLFT/ SLG8SP512T
ICS9LPRS365 RTM875T-606
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN
DREFSSCLK#_R RP42 1 2 IV@0X2
PCI2/TME DREFSSCLK# (6)
DREFSSCLK_R 3 4 To NB
Pin 4 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN DREFSSCLK (6)
10/31 REV_A1 Change Value
B PCI-3/SRC5_EN PIN37/38 IS B
3 4 CLK_MXM (19)
Pin 5 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) PCLK_PCM C311 *33p_4 1 2 To MXM
RP47 EV@0X2 CLK_MXM# (19)
PCLK_591 C312 *33p_4
PCI-4/27M_SEL PIN 17/18 CLKUSB_48 C324 15p_4
Pin 6 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) 14M_ICH C258 *33p_4
PCLK_ICH C323 *33p_4
PCIF-5/ITP_EN PCLK_DEBUG C304 *33p_4
Pin 7 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default)
Clock Gen
+3V
CPU Clock select (3) CPU_BSEL0
R282 0_4 CLK_BSEL0
MCH_BSEL0 (6) I2C Q17
RHU002N06 R242
2
R281 *56_4 10K_4
BSEL Frequency Select Table +1.05V
FSA (16,21,25,28) SDATA 3 1 CGDAT_SMB
FSC FSB FSA Frequency R280 *1K_4
+3V
0 0 0 266Mhz
Q18
RHU002N06 R250
2
0 0 1 133Mhz R225 0_4 CLK_BSEL1
(3) CPU_BSEL1 MCH_BSEL1 (6)
10K_4
3 1 CGCLK_SMB
(16,21,25,28) SCLK
0 1 1 166Mhz R227 *0_4
A
FSB A
0 1 0 200Mhz +1.05V R226 *1K_4 C685
*0.1u/10V_4
1 1 0 400Mhz +3V
01/21 REV_3B Add for ESD
R233 0_4 CLK_BSEL2
(3) CPU_BSEL2 MCH_BSEL2 (6)
1 1 1 Reserved
R234 *0_4 R261 10K_4 NEW_CLKREQ#_R
Quanta Computer Inc.
1 0 1 100Mhz FSC PROJECT : BL5S Santa Rosa
+1.05V R232 *1K_4 Size Document Number Rev
1A
1 0 0 333Mhz CLK. GEN./ CK505
Date: Tuesday, January 22, 2008 Sheet 2 of 37
5 4 3 2 1
5 4 3 2 1
U22A U19
(5) H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# (5)
CPU(HOST)
ADDR GROUP 0
H_A#4 L5 E2 THERM_MBCLK 8 1 LM86VCC
A[4]# BNR# H_BNR# (5) SCLK VCC
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# (5)
H_A#6 K5 THERM_MBDATA 7 2 H_THERMDA
H_A#7 A[6]# SDA DXP
M3 A[7]# DEFER# H5 H_DEFER# (5)
H_A#8 N2 F21 THERM_ALERT#_R 6 3 H_THERMDC
A[8]# DRDY# H_DRDY# (5) ALERT# DXN
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# (5)
H_A#10 N3 THER_SHD# 4 5
H_A#11 A[10]# OVERT# GND
P5 A[11]# BR0# F1 H_BREQ#0 (5)
H_A#12 P2 A[12]#
CONTROL
CPU Thermal monitor
H_A#13 L2 D20 H_IERR# R40 56.2_4 +1.05V LM95245
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# (14)
H_A#15 P1 12/06 REV_3A Add C666
H_A#16 A[15]# +3V
R1 A[16]# LOCK# H4 H_LOCK# (5)
D D
(5) H_ADSTB0# M1 ADSTB[0]#
C1 H_CPURST#
(5) H_REQ#[4:0] RESET# H_CPURST# (5)
H_REQ#0 K3 F3
REQ[0]# RS[0]# H_RS#0 (5)
H_REQ#1 H2 F4 01/17 REV_3B mount C666
REQ[1]# RS[1]#