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5 4 3 2 1
X'TAL
VCORE(ISL6262A) +1.2V/+1.25V/1.5V/2.5V
14.318MHZ
ZD1(CHAPALA) SYSTEM BLOCK DIAGRAM
CLOCK GENERATOR P33 P37
SELGO: SLG8SP512K05 CPU
Merom 479
5V/3.3V (ISL6236) BATTERYCHARGER
D P2 uFCPGA P3,P4 Thermal Sensor
P3
(ISL6251) D
P33 P32
TVOUT FSB 667/800 Mhz
DISCHARGE +1.8V / +1.05V
CRT P19
P37 P35,36
DDRII
Dual Channel DDR2 SO-DIMM 0
TFT LCD Panel VGA NB 533/667 MHz
WXGA LVDS
SO-DIMM 1
Crestline
WSXGA+ P16
WUXGA PM965
P18 PCI-Express 16X Lan
P5,P6,P7,P8,P9,P10,P11 DVI MXM-NB8P-GS USB6 USB5
LVDS ( nVidia )
HDD (SATA) X4 DMI interface VGA/TV out VRAM 256M Mini Card /
C
VRAM 512M New Card Robson
C
P24
P17
WLAN / 3G(TV)
SATA0 P22 P23 P29
SATA1 PCI-Express PCIE-2 PCIE-4 PCIE-1 PCIE-5
ODD (PATA) SB
PATA
P24
ICH8M PCI Bus PCIE-6
USB 2.0 X'TAL
Bluetooth Azalia
25M
USB4 P21 P12,P13,P14,P15 X'TAL24.576MHZ
X'TAL
USB Port x 4 32.768KHZ BROADCOM
USB0~3 P25
1394
10/100/1G LAN
+Cardreader
CCD Int MIC 5787M
USB7 P21 P27
Controller
B P20 B
R5C832/833
LPC
Azalia Audio X'TAL P28
Transformer
32.768K
Audio Amplifier Controller P20
P27 ALC268&888 P26 EC (WPC8769LDG)
RJ45
P31 P21
IEEE 1394 Port Media Card Reader Fan Header
P28 P28 P21,P30
MIC Jack Line in
P27 P27
SPI ROM
P31 VR
P26
Connector
BOM MARK
A Speaker Phone Jack MDC 1.5 Touch Pad EV@ EXT VGA A
P27 P27 P26
P30 CIR IV@ INT VGA
268@ AUDIO 268
P21 888@ AUDIO 888
PROJECT : ZD1
K/B COON. Quanta Computer Inc.
P30
Size Document Number Rev
Block Diagram E
Date: Wednesday, April 25, 2007 Sheet 1 of 38
5 4 3 2 1
5 4 3 2 1
Clock Generator
Change list:
B-test
1.Change U31 P/N to ALPRS365K13 (ICS)
+3V +3V
+3V R205 +3V_VDD_A
BKP1608HS181-T
C347 C349 C340 C352 C362 C342 C345 C339 R435 R443
*10K_4 *10K_4
4.7U/10V .1U/10V_4
.1U/10V_4 .1U/10V_4
.1U/10V_4 .1U/10V_4
.1U/10V_4
10U/6.3V
PCI_CLK_SIO PCLK_ICH
D D
R439 R207
10K_4 10K_4
+1.25V R220 +1.25V_VDD
BKP1608HS181-T
+3V_VDD_A U31
C355 C350 C375 C372 C353 C360 C359 C358
.1U/10V_4
4.7U/10V .1U/10V_4
.1U/10V_4 .1U/10V_4
.1U/10V_4 .1U/10V_4
10U/6.3V 2 12 +1.25V_VDD
0_4 R206 VDD_A_48 VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
16 VDD_PLL3 VDD_SRC_I/O_1 26
39 VDD_SRC VDD_SRC_I/O_2 36
55 VDD_CPU VDD_SRC_I/O_3 45
0_4 R431 VDD_A_REF 61 49
VDD_REF VDD_CPU_I/O
CPU_STOP# 37 PM_STPCPU# <14>
38 PM_STPPCI# <14> +3V R433 10K_4 PCLK_DEBUG
PCI_STOP#
CKPWRGD/PD# 56 CK_PWRGD <14>
CG_XOUT 59 54 CLK_CPU_BCLK_R RP42 1 2 0X2 MCH_BSEL0 R446 2.2K_4 CLKUSB_48
XTAL_OUT CPU_0 CLK_CPU_BCLK <3>
CG_XIN 60 53 CLK_CPU_BCLK#_R 3 4
XTAL_IN CPU_0# CLK_CPU_BCLK# <3>
<14> SATACLKREQ# R430 475_4 SATACLKREQ#_R 1 51 CLK_MCH_BCLK_R RP44 1 2 0X2
PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK <5>
R432 33_4 PCI_CLK_7412_R 3 50 CLK_MCH_BCLK#_R 3 4 MCH_BSEL2 R424 10K_4 FSC
<28> PCLK_PCM PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# <5>
R434 33_4 PCLK_MINI_R 4 47 PCIE_CLK_RBS_R RP46 1 2 0X2
<22,30> PCLK_DEBUG PCI_2 SRC_8/CPU_ITP PCIE_CLK_RBS <29>
R436 33_4 PCLK_591_R 5 46 PCIE_CLK_RBS#_R 3 4
<31> PCLK_591 PCI_3 SRC_8#/CPU_ITP# PCIE_CLK_RBS# <29>
PCI_CLK_SIO R440 33_4 PCI_CLK_SIO_R 6
R444 33_4 PCLK_ICH_R ^PCI_4/LCDCLK_SEL
<13> PCLK_ICH 7 PCIF_5/ITP_EN
C C
NC 48
R447 33_4 FSA 10
<14> CLKUSB_48 MCH_BSEL1 USB_48MHz/FS_A
C: For EMI solution 57 FS_B/TEST_MODE
17 CLK_DREFSSCLK_R RP45 3 4 IV@0X2
LCDCLK/27M CLK_DREFSSCLK <7>
Clock Gen I2C
14M_ICH 18 CLK_DREFSSCLK#_R 1 2
LCDCLK#/27M_SS CLK_DREFSSCLK# <7>
R423 33_4 FSC 62
<14> 14M_ICH REF/FS_C/TEST_SEL
C645
*30P/50V_4 RP43 4 3 IV@0X2 DREFCLK_R 13 21 CLK_PCIE_SATA_R RP47 3 4 0X2
<7> CLK_DREFCLK SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA <12>
2 1 DREFCLK#_R 14 22 CLK_PCIE_SATA#_R 1 2
<7> CLK_DREFCLK# SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# <12>
24 CLK_PCIE_LAN_R RP49 3 4 0X2
SRC_3/CLKREQ_C# CLK_PCIE_LAN <20>
CGCLK_SMB 64 25 CLK_PCIE_LAN#_R 1 2
SCL SRC_3#/CLKREQ_D# CLK_PCIE_LAN# <20>
CGDAT_SMB 63 27 CLK_PCIE_MINI1_R RP51 3 4 0X2
SDA SRC_4 CLK_PCIE_MINI1 <22>
28 CLK_PCIE_MINI1#_R 1 2 +3V
SRC_4# CLK_PCIE_MINI1# <22>
41 CLK_PCIE_ICH_R RP50 1 2 0X2
SRC_6 CLK_PCIE_ICH <13>
40 CLK_PCIE_ICH#_R 3 4
SRC_6# CLK_PCIE_ICH# <13>
44 PECLK_VGA_R RP48 1 2 EV@0X2
SRC_7/CLKREQ_F# CLK_MXM <17>
8 43 PECLK_VGA#_R 3 4
VSS_PCI SRC_7#/CLKREQ_E# CLK_MXM# <17>
11 30 CLK_PCIE_NEW_C_R RP53 3 4 0X2 Q27 R428 R429
VSS_48 SRC_9 CLK_PCIE_NEW_C <23>
15 31 CLK_PCIE_NEW_C#_R 1 2 RHU002N06
VSS_I/O SRC_9# CLK_PCIE_NEW_C# <23>
2
19 34 CLK_PCIE_3GPLL_R RP52 3 4 0X2 10K_4 10K_4
VSS_PLL3 SRC_10 CLK_PCIE_3GPLL <7>
23 35 CLK_PCIE_3GPLL#_R 1 2
VSS_SRC_1 SRC_10# CLK_PCIE_3GPLL# <7>
29 33 CLK_PCIE_TV_R RP36 3 4 0X2 3 1 CGDAT_SMB
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_PCIE_TV <22> <14,16,22,23> PDAT_SMB
42 32 CLK_PCIE_TV#_R 1 2
VSS_SRC_3 SRC_11#/CLKREQ_G# CLK_PCIE_TV# <22>
C563 33P/50V_4 CG_XIN 52 VSS_CPU
58 VSS_REF
+3V
XTAL length < 500mils Y4
14.318MHz Q28
ICS9LPRS365BGLFT RHU002N06
2
C565 33P/50V_4 CG_XOUT Main: ICS9LPRS365BGLFT:ALPRS365K13
B B
SLG8SP512T: AL8SP512K05 3 1 CGCLK_SMB
<14,16,22,23> PCLK_SMB
CPU Clock select <3> CPU_BSEL0
R455 0_4 MCH_BSEL0
MCH_BSEL0 <7>
BSEL Frequency Select Table
+1.05V R456 *56_4
FSC FSB FSA Frequency
R450 *1K_4
0 0 0 266Mhz
R451 0_4 MCH_BSEL1 0 0 1 133Mhz
<3> CPU_BSEL1 MCH_BSEL1 <7>
0 1 1 166Mhz
R449 *0_4
A A
0 1 0 200Mhz
+1.05V R454 *1K_4
1 1 0 400Mhz
R425 0_4 MCH_BSEL2
<3> CPU_BSEL2 MCH_BSEL2 <7>
1 1 1 Reserved
PROJECT : ZD1
R427 *0_4 1 0 1 100Mhz
Quanta Computer Inc.
+1.05V R426 *1K_4 1 0 0 333Mhz Size Document Number Rev
CLOCK GENERATOR CK505 W/REGULATOR E
Date: Monday, May 07, 2007 Sheet 2 of 38
5 4 3 2 1
5 4 3 2 1
U22A
<5> H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# <5>
CPU(HOST) CPU Thermal monitor
H_A#4
ADDR GROUP 0
L5 A[4]# BNR# E2 H_BNR# <5>
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# <5>
H_A#6 K5
H_A#7 A[6]# +3V +3V
M3 A[7]# DEFER# H5 H_DEFER# <5>
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# <5>
H_A#9 J1 E1 Q25
A[9]# DBSY# H_DBSY# <5>
2
H_A#10 N3 RHU002N06
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 <5>
H_A#12 P2 <31,32> MBCLK 3 1
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR# R79 56.2/F_4 +1.05V
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# <12>
H_A#15 P1
H_A#16 A[15]# +3V R360 R361 R357
R1 A[16]# LOCK# H4 H_LOCK# <5>
D D
<5> H_ADSTB0# M1 ADSTB[0]#
C1 Q26 10K_4 10K_4 200
<5> H_REQ#[4:0] RESET# H_CPURST# <5>
2
H_REQ#0 K3 F3 RHU002N06 LM86VCC
REQ[0]# RS[0]# H_RS#0 <5>
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 <5>
H_REQ#2 K2 G3 <31,32> MBDATA 3 1 C517
REQ[2]# RS[2]# H_RS#2 <5>
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# <5>
H_REQ#4 L1 .1U/10V_4
REQ[4]#
<5> H_A#[35:17] HIT# G6 H_HIT# <5>
H_A#17 Y2 E4 U24
A[17]# HITM# H_HITM# <5>
H_A#18 U5 H_THERMDA
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4 T8 8 SCLK VCC 1
H_A#20
ADDR GROUP 1
W6 AD3 XDP_BPM#1
A[20]# BPM[1]# T2
H_A#21 U4 AD1 XDP_BPM#2 7 2 C518
XDP/ITP SIGNALS
A[21]# BPM[2]# T3 SDA DXP
H_A#22 Y5 AC4 XDP_BPM#3
A[22]# BPM[3]# T6
H_A#23 U1 AC2 XDP_BPM#4 6 3 2200P/50V_4
A[23]# PRDY# T4 ALERT# DXN
H_A#24 R4 AC1 XDP_BPM#5
A[24]# PREQ# T5
H_A#25 T5 AC5 XDP_TCK <14,17> THERM_ALERT# R362 *0_4 4 5 H_THERMDC
H_A#26 A[25]# TCK XDP_TDI OVERT# GND
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS MAX6657
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST# ADDRESS: 98H
H_A#30 A[29]# TRST# XDP_DBRESET# R358 0_4
U2 A[30]# DBR# C20 SYS_RST# <14>
H_A#31 V4 +3V R363 *10K_4 CPUFAN#_ON
H_A#32 A[31]#
W3 A[32]# Layout Note:Routing 10:10 mils and away
H_A#33 AA4 THERMAL R355 56.2/F_4 +1.05V
H_A#34 AB2
A[33]# from noise source with ground gard
H_A#35 A[34]# <30> CPUFAN#_ON
AA3 A[35]# PROCHOT# D21 H_PROCHOT_R# R82 *2.2K_4
H_PROCHOT# <34>
<5> H_ADSTB1# V1 ADSTB[1]# THERMDA A24 H_T