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5 4 3 2 1
AMD Socket AM2 with AMD M690T
D
Chipset Reference Schematic D
NOTES: Page Index Page Index
------- -------------------------------------------- ------- --------------------------------------------
1) This schematic supports the AMD Socket AM2 CPU devices.
1 Cover Page 17 SB600 PCIe, PCI, LPC, Straps, & CPU Control
2) These are "Reference Schematics" and as such they have 2 Revision History 18 SB600 ACPI, GPIO, USB, and Audio Interfaces
not been verified by an actual board build. 3 Block Diagram 19 SB SATA, IDE, SPI, and HW Management Interfaces
3) This reference schematic supports AMD M960T revision 4 Clock Structure 20 SB600 Power
A12 or later. If A12 or later revision is not used, please 5 Power Configuration (1) 21 CRT Connector
see your customer support representative for the 6 Power Configuration (2) 22 Broadcom Ethernet Controller
necessary application notes for workarounds. 7 Reset & Voltage Sequence 23 Realtek Audio Codec
C 4) This reference schematic supports SB600 revision 8 Socket AM2 HT Interface 24 LPC BIOS C
A21 or later. If A21 or later revision is not used, please 9 Socket AM2 DDRII Memory Interface 25 USB Power and Connectors
see your customer support representative for the 10 Socket AM2 Control & Debug 26 Power Main System, SB600 PCIe, & Other
necessary application notes for workarounds. 11 Socket AM2 Power & Ground 27 Standby Power & Powergood
5) Unless otherwise specified, resistors have 5% tolerance. 12 SODIMM DDR2 28 Power for CPU Core
13 M690T HT, PCI, PCIe(R), PCIe Graphics Port 29 Power for DDR2 Memory and Interface
6) Unless otherwise specified, capacitors have 20% tolerance.
14 M690T PLL and Video Interface 30 Power M690T Core, PCIe Interface
15 M690T Power and Side Port Memory Interface 31 Unused Interfaces
16 Clock Generator
IMPORTANT NOTICE:
B 1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENT B
AND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULD
CONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE, OR
PROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOMMENDATIONS AND PCB LAYOUT
GUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAM
AND PCB LAYOUT BEFORE CONSIDERING PRODUCTION.
2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOUT NOTICE. DESIGN CONSIDERATIONS
CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,
WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR A DESIGN NOTE:
PARTICULAR USE. Example text for informational
design notes .
3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESS
FOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PERFORMANCE,
OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION. DESIGN NOTE:
Example text for cautionary
4. AMD'S PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED FOR USE AS design notes.
COMPONENTS IN SYSTEMS INTENDED FOR SURGICAL IMPLANT INTO THE BODY, OR IN OTHER
APPLICATIONS INTENDED TO SUPPORT OR SUSTAIN LIFE, OR IN ANY OTHER APPLICATION IN
A
WHICH THE FAILURE OF AMD'S PRODUCT COULD CREATE A SITUATION WHERE PERSONAL DESIGN NOTE: A
INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE MAY OCCUR. Example text for critical
design notes.
*AMD CONFIDENTIAL*
(c)2007 AMD, THE AMD ARROW LOGO, AND COMBINATIONS THEREOF, AND AMD SMARTER Advanced Micro Devices
1351 South Sunset St.
CHOICE LOGO ARE TRADEMARKS OF ADVANCED MICRO, DEVICES INC. HYPERTRANSPORT Longmont, CO 80501
IS A LICENSED TRADEMARK OF HYPERTRANSPORT TECHNOLOGY CONSORTIUM. PCIE IS A LAYOUT NOTE:
REGISTERED TRADEMARK OF PCI-SIG. OTHER NAMES USED IN THIS PUBLICATION ARE FOR Example text for critical
Title
AMD_AM2 / AMD M690T Reference Schematic
IDENTIFICATION PURPOSES ONLY AND MAY BE TRADEMARKS OF THEIR RESPECTIVE layout guidelines. PID
42684 Rev
0.5
OWNERS. Cover page Size Date: Sheet
1 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
REVISION HISTORY:
REV DATE NOTES
------- ----------------- ----------------------------------------------------------------------------------
0.5 04/20/2007 Preliminary release
D D
C C
B B
A A
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Revision History Size Date: Sheet
2 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
REFERENCE DESIGN FOR SOCKET S1 / M690T / SB600
AMD AM2 PROCESSOR UNBUFFERED DDR2
D DDR2 400/533/667 DIMM D
EXTERNAL CLOCK GENERATOR 961-Pin uFCPGA 12
8,9,10,11
200-PIN DDR2 SODIMM
HT
OUT
ICS951462 16x16
LINK0
IN
16
LVDS I/F
AMD NB - M690T
DDR2 400/533/667/800 Not Connected
HyperTransportTM LINK0
TV (SVIDEO/COMP/HD) I/F
INTEGRATED GRAPHICS
DDR2 MEMORY (X16)
CRT I/F LVDS/TVOUT/TMDS
1 X8 PCIETM VIDEO/DDP2 I/F
1 X4 PCIE I/F WITH SB
1 X8 PCIE I/F
3 X1 PCIE I/F
C C
3 X1 PCIE INTERFACE 13,14,15
A-LINK (PCIE)
10/100/1000M PCIE(R) ETHERNET 1x PCIE X4
X1 22
AMD SB - SB600
8 X USB 2.0 I/F USB2.0 (10)
AC LINK / HD AUDIO I/F
SATA II (4 PORTS)
AZALIA HD AUDIO
AC97 2.3
SATA I/F
ATA 66/100/133
SPI I/F
B LPC I/F
ATA 66/100/133 I/F
B
ACPI 1.1
INT RTC
HW MONITOR
SYSTEM MANAGEMENT I/F
PCI/PCI BDGE
PCI BUS I/F 17,18,19,20
LPC BUS
FLASH BIOS
CPU CORE POWER CPU MEMORY POWER
28 29 24
A A
M690T CORE &
30
SB600 & PCIE POWER SYSTEM POWER, *AMD CONFIDENTIAL*
PCIE POWER 26 +5V/3.3V 26
Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Block Diagram Size Date: Sheet
3 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
D D
PCI CLK
33MHZ
LPC_CLK
33MHZ
HTREFCLK AC_BITCLK
66MHZ
NB - M690T
NB_OSC SB600
14.318MHZ
DIMM
2 PAIR MEM CLK
1 PAIR NBSRC_CLK
C C
100MHZ
SBLINK
100MHZ
EXTERNAL
CLK GEN.
PCIE_CLK_REF
100MHZ
1 PAIR CPUCLK ROM_CLK
SOCKET AM2 CPU LPC BIOS
25M Hz
200MHZ 33MHZ
GPP_CLK
GIGABIT ETHERNET - 1 LANE
100MHZ
SBSRC_CLK
100MHZ
CLK_14_CODEC
25M Hz
14.318MHZ AC97 CODEC
B B
USB CLK
48MHZ
SB_OSCIN
32.768K Hz
14.318MHZ
14.31818MHz
A A
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Clock Structure Size Date: Sheet
4 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
POWER RAIL POWER RAIL
D
SOURCE NET V (NET NAME) S0 S1 S3 S4 S5 SOURCE NET V (NET NAME) S0 S1 S3 S4 S5 D
INPUT RS690T VCC1P8V +1.8V (PLLVDD18) ON ON OFF OFF OFF
VOLTAGE VCC_12V +12V ON ON OFF OFF OFF
VCC1P8V +1.8V (LVDDR18,LPVDD) ON ON OFF OFF OFF
VCC1P8V +1.8V (VDD_18) ON ON OFF OFF OFF
VCC3P3V_ALW +3.3V ON ON ON ON ON
SYSTEM VCC1P8V +1.8V (HTPVDD) ON ON OFF OFF OFF
POWER VCC1P2V_ALW +1.2V ON ON ON ON ON
VCC1P8V +1.8V (AVDDI) ON ON OFF OFF OFF
VCC3P3V_DUAL +3.3V ON ON ON ON ON
VCC1P8V +1.8V (AVDDQ) ON ON OFF OFF OFF
VCC5V +5V ON ON OFF OFF OFF
VCC3P3V +3.3V (VDDR3,LVDDR33) ON ON OFF OFF OFF
VCC3P3V +3.3V ON ON OFF OFF OFF
VCC3P3V +3.3V (AVDD) ON ON OFF OFF OFF
CPU CPU_VDD_RUN VID[5:0] ON ON OFF OFF OFF
SB600 VCC1P2V_SB +1.2V (VDD) ON ON OFF OFF OFF
VCC1P2V +1.2V ON ON OFF OFF OFF
VCC1P2V_SB +1.2V(PCIE_PVDD) ON ON OFF OFF OFF
CPU_VDDA_RUN +2.5V ON ON OFF OFF OFF
VCC1P2V_SB +1.2V(PCIE_VDDR) ON ON OFF OFF OFF
CPU & CPU_VDDIO_SUS +1.8V ON ON ON OFF OFF VCC1P2V_SB +1.2V(PLLVDD_SATA) ON ON OFF OFF OFF
MEMORY CPU_M_VREF_SUS +0.9V ON ON ON OFF OFF VCC1P2V_SB +1.2V(AVDD_SATA) ON ON OFF OFF OFF
C C
MEM_M_VREF_SUS +0.9V ON ON ON OFF OFF VCC1P2V_SB +1.2V (AVDDCK_1.2V) ON ON OFF OFF OFF
CPU_VTT_SUS +0.9V ON ON ON OFF OFF VCC1P2V_ALW +1.2V (S5_1.2V) ON ON ON ON ON
VCC1P2V_ALW +1.2V(USN_PHY_1.2V) ON ON ON ON ON
RS690T VCC1P2V_NB +1.2V (VDDC) ON ON OFF OFF OFF
VCC3P3V_DUAL+3.3V (AVDDC) ON ON ON ON ON
VCC1P2V +1.2V (VDDA_12) ON ON OFF OFF OFF
VCC3P3V +3.3V(XTLVDD_SATA) ON ON OFF OFF OFF
VCC1P2V +1.2V (VDD_HT) ON ON OFF OFF OFF
VCC3P3V +3.3V (VDDQ) ON ON OFF OFF OFF
VCC1P2V +1.2V (VDDPLL) ON ON OFF OFF OFF
VCC3P3V +3.3V (AVDD) ON ON OFF OFF OFF
VCC1P2V +1.2V (PLLVDD12) ON ON OFF OFF OFF
VCC3.3V_ALW +3.3V (S5_3.3V) ON ON ON ON ON
VCC3P3V_DUAL+3.3V (AVDDTX_RX) ON ON ON ON ON
VCC3P3V +3.3V (AVDDCK_3.3V) ON ON OFF OFF OFF
VCC1P8V +1.8V (CPU_PWR) ON ON OFF OFF OFF
VCC5V +5V (V5_VREF) ON ON OFF OFF OFF
B POWER ON SEQUENCING REQUIREMENT BY PARTS B
CPU
PIN(BALL): VDDIO & VTT & VDDA -> VDD -> VLDT
NET NAME: CPU_VDDIO_SUS & CPU_VTT_SUS & CPU_VDDA_RUN -> CPU_VDD_RUN -> VCC1P2V
RS690T
PIN(BALL): 3.3V (VDDR3, LVDDR33, AVDD) -> 1.8V DISIPLAY AND PLL(PLLVDD18, IOPLLVDD18, LVDDR18D, LPVDD, AVDDI, AVDDQ, HTPVDD, VDD_18)
--> 1.8V MEMORY(VDD_MEM) -> 1.2V PLL (PLLVDD12, IOPLLVDD12) -> 1.2V VDD
NET NAME: VCC3P3V (VDDR3, LVDDR33, AVDD) -> VCC1P8V (PLLVDD18D, IOPLLVDD18, LVDDR18D, LPVDD, AVDDDI, AVDDQ, HTPVDD, VDD_18) -->
MEM_VDDQ (VDD_MEM) -> VCC1P2V (PLLVDD12, IOPLLVDD12) -> VCC1P2V_NB
THERE ARE NO SPECIFIC REQUIREMENTS FOR THE FOLLOWING 1.2V RAILS: VDD_HT, VDDA_12, AND VDD_PLL
SB600
THERE ARE NO SPECIFIC POWER SEQUENCING REQUIREMENTS OTHER THAN 5V VREF AND VDDQ. VDDQ(3.3V) MUST NOT EXCEED V5_VREF BY MORE THAN 0.6V
AT ANY TIME DURING RAMP UP, STEADY STATE, OR RAMP DOWN.
NET NAME: VCC5V, VCC3P3V -> VCC1P2V_SB
A A
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Power Configuration (1) Size Date: Sheet
5 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
VCC5V 2.5V LDO CPU_VDDA_RUN (S0, S1)
VCC_12V REGULATOR AMD SOCKET AM2
D
VCC_12V VCCA 2.5V 500mA D
SW REGULATOR CPU_VDD_RUN (S0, S1) VDDCORE
Generic VCC5V
0.375-1.500V 35A
VCC3P3V
Power VCC_12V MAIN PWR SW
Supply REGULATOR VCC5V
VLDT 1.2V 0.5A
NB M690T
12V @ 7A VCC_12V HT VLDT 1.2V 0.5A
5V STANDBY NB CORE SW VCC1P2V_NB (S0, S1) NB CORE 5A
REGULATOR VCC5V REGULATOR
(3A) PCI-E CORE
&PCI-E IO 5A
VCC_5V_STB VCC_5V_STB VCC1P2V (S0, S1) HTPLL (1.8V) 200mA
PLL & DAC-Q(1.8V)
200mA
+3.3VALW LDO VCC3P3V_ALW VCC1P8V (S0, S1) TRANSFORMER
Switch
REGULATOR 400mA
VCC3P3V VCC3P3V (S0, S1) DAC 300mA
VCC3P3V_DUAL
C
Switch Filter C
VCC3P3V
DDR2 SODIMMX2
CPU_VDDIO_SUS (S0, S1, S3)
1.8V VDD&VTT VDD MEM 3A
VCC12V SW REGULATOR CPU_VTT_SUS (S0, S1, S3)
VTT_MEM 1A
VCC1P2V_SB (S0, S1)
SB SB600
X4 PCI-E 0.8A
ATA I/O 0.2A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
VCC3P3V_ALW 1.2V LDO VCC1P2V_ALW 1.2V S5 PW 0.22A
VCC3P3V REGULATOR
PCI DEVICES IRQ TABLE 3.3V I/O 0.45A
B
DEVICE IDSEL# REQ/GNT# PCI INT CLOCK VCC3P3V_DUAL 3.3V S5 PW 0.01A B
USB CORE I/O 0.2A
M690T VGA N/A N/A A
SB600 AD31(INT) N/A N/A
GBIT ETHERNET
ATA AD31 N/A A INT
3.3V 0.5A
AC97/HD AD31 N/A B INT
(S0, S1, S3, S4, S5)
USB AD30 N/A D INT
FLASH ROM
3.3V 0.1A
SMBUS TABLE
SOURCE BALL(PIN) NAME LINKED DEVICES
CLOCK CHIP
M690T DACSCL/DACSDA CRT
3.3V 0.4A
I2C_CLK/I2C_DATA LVDS DEFAULT JUMPER SETTING FOR POWER ON
A
JUMPER DEF. FUNCTION A
SB600 SCL0/SDA0 SO-DIMM / CLK_GEN /
THERM_SENSOR JU5 1-2 CMOS NORMAL MODE OR CLEAR CMOS *AMD CONFIDENTIAL*
JU7 1-2 SPI BIOS PROGRAMMING SELECTION
SCL1/SDA1 GBIT ETHERNET Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Power Configuration (2) Size Date: Sheet
6 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
D D
POWER ON/OFF SEQUENCE
Subsystem or Part G3 S5 S0 S3 S5 G3
NET NAME
Power Supply Input
PWR_OK
=== FOR CPU ===
* VDIMM_DUAL_EN
* VDDA_EN
CPU_VDDA_RUN_PWRGD
VMEM_PWRGD
* CPU_VDD_EN
C C
CPU_VDD_PWR_GD
* VLDT_EN
VLDT_PWRGD
=== FOR RS960T ===
VCC_NB_PWRGD &
VDDA_1V2PWRGD
NB_PWRGD
SB_PWRGD
CPU_PWRGD
CPU_LDT_RST#
EXT CLKx
Power Supply Input Voltages
VCC_5V_SBY
VCC_12V
Board Power
B VCC5V, +5V B
VCC3P3V, +3.3V
AMD CPU Power
CPU_VDDIO_SUS/VTT
CPU_VDDA_RUN
CPU_VDD_RUN
VCC1P2V
NB M690T Power
VCC5V, +5V
VCC1P8V, MEM_VDDQ
VCC1P2V
VDD1P2V. +1.2V
VCC1P2V_NB, +1.2V
SB SB600 Power
VCC3P3V_ALW
VCC3P3V_DUAL
VCC1P2V_ALW
VCC5V, +5V
VCC3P3V, +3.3V
VCC1P8V, +1.8V
VCC1P2V_SB, +1.2V
G3 S5 S0 S3 S5 G3
A A
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont, CO 80501
Title
AMD_AM2 / AMD M690T Reference Schematic
PID Rev
42684 0.5
Reset and Voltage Sequence Size Date: Sheet
7 31
Custom Friday, April 20, 2007 of
5 4 3 2 1
5 4 3 2 1
DESIGN NOTE: VLDT_Ax or VLDT_Bx can be connected to VCC1P2V.
Layout considerations should decide which group is connected to
VCC1P2V. If VLDT_Ax pins are connected to VCC1P2Vthen VLDT_Bx pins
should be connected to a single 4.7uF CAP. Conversely, if VLDT_Bx pins
are connected to VCC1P2Vthen VLDT_Ax pins should be connected to a
D single 4.7uF CAP. D
VLDT_RUN
U1A
AJ4 H6 C1 4.7uF
VLDT_06 VLDT_08
AJ3 VLDT_05 VLDT_07 H5
AJ2 VLDT_02 VLDT_04 H2
AJ1 VLDT_01 VLDT_03 H1
13 HT_CADIN15_P U6 L0_CADIN_H15 L0_CADOUT_H15 Y5 HT_CADOUT15_P 13
13 HT_CADIN15_N V6 L0_CADIN_L15 L0_CADOUT_L15 Y4 HT_CADOUT15_N 13
13 HT_CADIN14_P T4 L0_CADIN_H14 L0_CADOUT_H14 AB6 HT_CADOUT14_P 13
13 HT_CADIN14_N T5 L0_CADIN_L14 L0_CADOUT_L14 AA6 HT_CADOUT14_N 13
13 HT_CADIN13_P R6 L0_CADIN_H13 L0_CADOUT_H13 AB5 HT_CADOUT13_P 13
13 HT_CADIN13_N T6 L0_CADIN_L13 L0_CADOUT_L13 AB4 HT_CADOUT13_N 13
13 HT_CADIN12_P P4 L0_CADIN_H12 L0_CADOUT_H12 AD6 HT_CADOUT12_P 13
13 HT_CADIN12_N P5 L0_CADIN_L12 L0_CADOUT_L12 AC6 HT_CADOUT12_N 13
13 HT_CADIN11_P M4 L0_CADIN_H11 L0_CADOUT_H11 AF6 HT_CADOUT11_P 13
13 HT_CADIN11_N M5 L0_CADIN_L11 L0_CADOUT_L11 AE6 HT_CADOUT11_N 13
13 HT_CADIN10_P L6 L0_CADIN_H10 L0_CADOUT_H10 AF5 HT_CADOUT10_P 13
13 HT_CADIN10_N M6 L0_CADIN_L10 L0_CADOUT_L10 AF4 HT_CADOUT10_N 13
13 HT_CADIN9_P K4 L0_CADIN_H9 L0_CADOUT_H9 AH6 HT_CADOUT9_P 13
13 HT_CADIN9_N K5 L0_CADIN_L9 L0_CADOUT_L9 AG6 HT_CADOUT9_N 13
13 HT_CADIN8_P J6 L0_CADIN_H8 L0_CADOUT_H8 AH5 HT_CADOUT8_P 13
13 HT_CADIN8_N K6 L0_CADIN_L8 L0_CADOUT_L8 AH4 HT_CADOUT8_N 13
HT LINK
13 HT_CADIN7_P U3 L0_CADIN_H7 L0_CADOUT_H7 Y1 HT_CADOUT7_P 13
13 HT_CADIN7_N U2 L0_CADIN_L7 L0_CADOUT_L7 W1 HT_CADOUT7_N 13
C R1 AA2 C
13 HT_CADIN6_P L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUT6_P 13
13 HT_CADIN6_N T1 L0_CADIN_L6 L0_CADOUT_L6 AA3 HT_CADOUT6_N 13
13 HT_CADIN5_P R3 L0_CADIN_H5 L0_CADOUT_H5 AB1 HT_CADOUT5_P 13
13 HT_CADIN5_N R2 L0_CADIN_L5 L0_CADOUT_L5 AA1 HT_CADOUT5_N 13
13 HT_CADIN4_P N1 L0_CADIN_H4 L0_CADOUT_H4 AC2 HT_CADOUT4_P 13
13 HT_CADIN4_N P1 L0_CADIN_L4 L0_CADOUT_L4 AC3 HT_CADOUT4_N 13
13 HT_CADIN3_P L1 L0_CADIN_H3 L0_CADOUT_H3 AE2 HT_CADOUT3_P 13
13 HT_CADIN3_N M1 L0_CADIN_L3 L0_CADOUT_L3 AE3 HT_CADOUT3_N 13
13 HT_CADIN2_P L3 L0_CADIN_H2 L0_CADOUT_H2 AF1 HT_CADOUT2_P 13
13 HT_CADIN2_N L2 L0_CADIN_L2 L0_CADOUT_L2 AE1 HT_CADOUT2_N 13
13 HT_CADIN1_P J1 L0_CADIN_H1 L0_CADOUT_H1 AG2 HT_CADOUT1_P 13
13 HT_CADIN1_N K1 L0_CADIN_L1 L0_CADOUT_L1 AG3 HT_CADOUT1_N 13
13 HT_CADIN0_P J3 L0_CADIN_H0 L0_CADOUT_H0 AH1 HT_CADOUT0_P 13
13 HT_CADIN0_N J2 L0_CADIN_L0 L0_CADOUT_L0 AG1 HT_CADOUT0_N 13
13 HT_CLKIN1_P N6 L0_C