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A B C D E
1 1
Compal confidential
2
Low Cost Los Angeles 10AL+ 2
NBWAE LA-5831P Schematics Document
Mobile AMD S1G2
RS780MN & RS780MC / SB700
3
2009-08-12 Rev. 1.0 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2009-02-12 2009-02-12 Title
Issued Date Deciphered Date Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5831P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 12, 2009 Sheet 1 of 44
A B C D E
A B C D E
Compal Confidential Memory BUS(DDRII) Thermal Sensor Clock Generator
Fan Control AMD S1G2 CPU Dual Channel ADM1032ARMZ page 7 SLG8SP626 page 16
page 5
Model Name : NBWAE
uFCPGA-638 Package 1.8V DDRII 667/800MHZ
File Name : LA-5831P page 5,6,7.8
200pin DDRII-SO-DIMM X2
1 Hyper Transport Link 2.6GHz BANK 0, 1, 2, 3 page 9,10 1
16X16
CRT
page 17
ATI
RTL8103E LAN 10/100M RJ45
RS780MN PCIe port 3 page 26
page 26
LCD Conn. PCIe 4x
page 18 RS780MC
1.5V 2.5GHz(250MB/s)
PCIe Mini Card WLAN
PCIe Port 2
HDMI Conn. PCIE-Express 4X
USB Port 8 page 27
page 19
page 11,12,13,14.15
2 2
A-Link Express II
4X PCI-E USB/B Right USB/B Left
USB port 0,1 USB port 2
page 25 page 25
USB 3IN1 Card Reader Int. Camera
5V 480MHz USB port 9
RTS5159-VDD
USB port 4 page 18
ATI page 28
SB700 SATA port 1 SATA HDD
5V 1.5GHz(150MB/s) page 25
SATA port 3 SATA ODD
5V 1.5GHz(150MB/s) page 25
page 20,21,22,23,24
3 3
HD Audio 3.3V 24.576MHz/48Mhz
LPC BUS
3.3V 33 MHz
MDC 1.5 Conn HDA Codec
Debug Port ALC272
page 31 page 29
ENE KB926D3
page 31 page 32
RTC CKT.
page 20
NBWAE Sub-boards RJ11 MIC Conn Int. MIC Conn HP Conn AMP.
page 31
Touch Pad Int.KBD SPI ROM page 30 page 30 page 30 TPA6017
page 33 page 31 page 31 page 30
Power On/Off CKT. Power/B
page 33
LS-4574P page 33
SPK Conn
page 30
DC/DC Interface CKT. Cap Sensor/B
4 4
page 34
LS-5822P page 33
USB/B
Power Circuit DC/DC LS-5821P page 25
page 35,36,37,38
39,40,41.42
Security Classification
2009-02-12
Compal Secret Data
2009-02-12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5831P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 12, 2009 Sheet 2 of 44
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5 4 3 2 1
DESIGN CURRENT 100mA +3VL
B+ DESIGN CURRENT 100mA +5VL
Ipeak=5A, Imax=3.5A, Iocp min=7.9 +5VALW
SUSP#
N-CHANNEL DESIGN CURRENT 5A +5VS
SI4800BDY
D D
Ipeak=5A, Imax=3.5A, Iocp min=7.7 +3VALW
SUSP#
TPS51125RGER N-CHANNEL DESIGN CURRENT 5A +3VS
SI4800BDY
UMA_ENVDD
P-CHANNEL DESIGN CURRENT 1.0A +LCD_VDD
AO-3413
SUSP
LDO DESIGN CURRENT 2A +1.5VS
APL5331KAC
WOL_EN#
DESIGN CURRENT 330mA +3V_LAN
P-CHANNEL
AO-3413
C C
DESIGN CURRENT 500mA +2.5VS
LDO
APL5508
POK
Ipeak=5A, Imax=3.5A, Iocp min=7.78 +1.2VALW
VLDT_EN
N-CHANNEL DESIGN CURRENT 4.5A +1.2V_HT
IRF8113PBF
TPS51124RGER
Ipeak=7A, Imax=4.9A, Iocp min=9.32 +NB_CORE (+1.1VS)
SUSP#
CPU_VCORE_ENABLE
B Ipeak=18A, Imax=12.6A, Iocp min=30 +CPU_CORE0 B
Ipeak=18A, Imax=12.6A, Iocp min=30 +CPU_CORE1
ISL6265 DESIGN CURRENT 4A +VDDNB
SYSON
Ipeak=8A, Imax=5.6A, Iocp min=8.87 +1.8V
TPS51117RGYR SUSP#
N-CHANNEL DESIGN CURRENT 1A +1.8VS
IRF8113PBF
SYSON#
LDO DESIGN CURRENT 2A +0.9V
APL5331KAC
A A
Security Classification
2009-02-12
Compal Secret Data
2009-02-12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5831P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 12, 2009 Sheet 3 of 44
5 4 3 2 1
A B C D E
Voltage Rails
O : ON Platform CPU NB SB
X : OFF S1G2 RS780MC SB700
PUMA@
S1G2 RS780MN SB700
S1G3 RS880MC SB710
TIGRIS@
S1G3 RS880M SB710
1
+5VS 1
power
plane +3VS
+2.5VS
+1.8VS
+1.5VS
B+ +5VALW +1.8V @ : just reserve , no build
+1.1VS
+3VL +3VALW +0.9V
+1.2V_HT
+5VL +1.2VALW BTO (Build-To-Order) Option Table
State +VDDNB
+RTCVCC +3V_LAN
+CPU_CORE_0
+CPU_CORE_1
Function Modem HDMI CAMERA & MIC
Description (R) (Y) (X)
Explain CAMERA MIC
S0 O O O O
BTO MDC@ HDMI@ CAM@ MIC@
S1 O O O O
2 2
S3 O O O X
S5 S4/AC O O X X
S5 S4/ Battery only O X X X
SMBUS Control Table
S5 S4/AC & Battery
don't exist X X X X CPU LCD HDMI
SOURCE INVERTER BATT HDMI SODIMM CLK WLAN DDC DDC NEW
CEC THERMAL GEN CARD
I / II ROM ROM
SENSOR
EC_SMB_CK1
KB926
SB700 SM Bus0 Address SB700 SM Bus1 Address EC_SMB_DA1 V
EC_SMB_CK2
KB926
EC_SMB_DA2 V
Power Device HEX Address Power Device HEX Address
I2C_CLK RS780MN
3
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b +3VALW WLAN/WIMAX I2C_DATA RS780MC V 3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b DDC_CLK0 RS780MN
+3VS Clock Generator D2 H 1101 0010 b DDC_DATA0 RS780MC V
DDC_CLK1 RS780MN
DDC_DATA1 RS780MC
SCL0
SB700
SDA0 V V
SCL1
KB926 SM Bus1 Address KB926 SM Bus2 Address SB700
V
SDA1
SCL2
Power Device HEX Address Power Device HEX Address SB700
SDA2
+3VL Smart Battery 16 H 0001 011X b +3VS CPU_ADM1032-1 98 H 1001 100X b SCL3
SB700
SDA3
KB926 ESB Address
4 Power Device HEX Address 4
+3VL Cap. Sensor Virtual I2C
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5831P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 12, 2009 Sheet 4 of 44
A B C D E
A B C D E
+1.2V_HT
VLDT CAP. Near CPU Socket
250 mil
1 1 1 1 1 1
PUMA@ TIGRIS@ PUMA@ TIGRIS@ C3 C4 C5 C6
C1 C1 C2 C2
4.7U_0805_10V4Z 10U_0805_10V6K 4.7U_0805_10V4Z 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
1 1
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
+1.2V_HT JCPUA PUMA@
C7
D1 HT LINK AE2 +VLDT_B 1 2 4.7U_0805_10V4Z
VLDT=500mA D2
VLDT_A0 VLDT_B0
AE3
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A1 VLDT_B1
D3 AE4
VLDT_A2 VLDT_B2 TIGRIS@
D4 VLDT_A3 VLDT_B3 AE5
C7
H_CADIP0 E3 AD1 H_CADOP0 10U_0805_10V6K
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 AC3
H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1
H_CADIN2 G2 AA1 H_CADON2
H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3
G1 AA2
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 AA3
2 H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 T4
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 T3
L0_CADIN_L15 L0_CADOUT_L15
<11> H_CLKIP0 J3 Y1 H_CLKOP0 <11>
L0_CLKIN_H0 L0_CLKOUT_H0
<11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>
<11> H_CLKIP1 J5 Y4 H_CLKOP1 <11>
L0_CLKIN_H1 L0_CLKOUT_H1
<11> H_CLKIN1 K5 Y3 H_CLKON1 <11>
L0_CLKIN_L1 L0_CLKOUT_L1
<11> H_CTLIP0 N1 R2 H_CTLOP0 <11>
L0_CTLIN_H0 L0_CTLOUT_H0
<11> H_CTLIN0 P1 R3 H_CTLON0 <11>
3 L0_CTLIN_L0 L0_CTLOUT_L0 3
<11> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <11>
<11> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <11>
6090022100G_B @
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
1
D1
2 @
+FAN1 C183 1SS355_SOD323-2
JFAN @ +3VS
1
2
C192 10U_0805_10V4Z +FAN1 1
1 1
2 2
1
1
10U_0805_10V4Z 2 3
2 U6 D2 C9 3 R12
1 8 @ @ 4
EN GND BAS16_SOT23-3 1000P_0402_25V8J GND 10K_0402_5%
2 7 5
VIN GND 1 GND
3 6
2
2
VOUT GND ACES_85204-0300N
< From EC ><32> EN_DFAN1 4
VSET GND
5 FAN_SPEED1 <32> < To EC >
2
APL5607KI-TRG_SO8 C8
4 @ 4
0.01U_0402_25V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5831P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 12, 2009 Sheet 5 of 44
A B C D E
A B C D E
< Processor DDR2 Memory Interface >
< DDR2 VREF is 0.5 ratio > < PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > JCPUC
<9> DDR_B_D[63..0]
+1.8V MEM:DATA
DDR_A_D[63..0] <10>
DDR_A_CLK0 DDR_B_CLK0 < From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1
1 1 A11
MB_DATA1 MA_DATA1