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8 7 6 5 4 3 2 1
INTEL (R) 850 CHIPSET
D
MS-6546 Pentium(R) 4 PROCESSOR in 478-Pin SCHEMATICS
D
Title Page Title Page
Cover Sheet 1 PCI Connectors 21,22,23
Block Diagram 2,3,4,5 VID 24
C C
Processor Sockets 6,7 Audio 25,26
Clock Synthesizer 8 CNR 27
DRCG 9 LPC/Flopy Connector 28
MCH 10,11,12 Hardware Monitor 29
SCK/CMD 12 Parallel Port/Serial Port 30
RIMM 13,14 KeyBoard/Mouse Ports 31
AGP 15 PC-PC 32
ICH2 16,17 Pull-up Resistors 33
FWH 18 Front Pannel 34
B IDE Connectors 19 VRM 9.0 35 B
USB Connectors 20 Voltage Regulator 36
Diagnostic LED 37
LAN 41
A A
Pentium(R) 4 Mother Board
Title
COVER
Size Document Number Rev
Custom MS-6546 0A
Date: Saturday, September 22, 2001 Sheet 1 of 39
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8 7 6 5 4 3 2 1
D D
14.318MHz SIO
14.318MHz SUSCLK
LAN_CLK FNT/LSB
CK00
33MHz PCI_Slot_5 EE_CLK LAN
3.3 volt 33MHz PCI_Slot_4 32.7kHz ICH
33MHz PCI_Slot_3 MS/KB
33MHz PCI_Slot_2 24.5MHz AUDIO CNR CON
33MHz PCI_Slot_1
CODEC
33MHz AUD_BCLK SMBCLK SMBCLK AUD_BCLK
AUDIO KBCLK
33MHz MCLK
33MHz
33MHz
C FWH C
33MHz
POC PLD GLUE
48MHz Pulled_up
3.3 volt
48MHz AGP CON SMBCLK HECETA
Hardware Management
66MHz HCLKOUT0
RCLKOUT0
66MHz HCLKOUT1
RCLKOUT1
66MHz MCH
66MHz DRCG1
DRCG2
3MREF_B 50/67MHz RIMM2
400MHz
Output RIMM0
3MREF 50/67MHz
3.3 volt MEM CLK DRCG_CTM*
14.318MHz DRCG_CTM1 SCL
SCL RIMM4
(Half Host CLK) RIMM1
B CPU B
100MHz CPU_CK
SMBCLK SCL
100MHz ITP_CK ITP Port SCL
Host Clock Pairs
100MHz MCH_CK
100MHz Pulled_up
A A
Title
Clock Distribution
Size Document Number Rev
CustomMS-6546 0A
Date: Saturday, September 22, 2001 Sheet 2 of 39
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D D
Power
Supply VRM Socket 478 CK_SKS Clock
CONN
Scalable Bus Scalable Bus/2
AGP 4X 4X (266MHz) AGP Sync Clock (2) DRCG 1&2
AGP MCH: Memory 400MHz DIFF CLK
CONN 400MHz DIFF CLK
Controller HUB
VRM Direct RDRAM Channel A RIMM SKTS 1:2
AGP Direct RDRAM Channel B
CONN
RIMM SKTS 3:4
HUB Interface
C Heceta Hardware SM Bus C
Monitor PCI (33MHz)
ICH2: I/O
PCI Slots 1:5
Controller HUB
IDE CONN 1&2 AC '97
Digital
Central
LPC Bus AC Link
USB Port 1:3 CNR Riser
(Shared slot)
AC '97 Audio
USB Port 4 FWH: Firmware HUB AMP
FRNL Panel Codec
SMC I/O
Line Out
Tehama Chipset Telephone In
MIC In
Audio In
B LAN B
Line In
PS2 Mouse & Parallel (1) Floppy Disk Stuffing
Keyboard Serial (1) Drive CONN Options CD-ROM
RJ45
A A
Title
Block Diagram
Size Document Number Rev
CustomMS-6546 0A
Date: Saturday, September 22, 2001 Sheet 3 of 39
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D VCC12 D
INTERSIL 3-PHASE VCORE
CONVERTER
SC1547 VCC1.8
VCC3
& MOSFET
C
SC1547 VDDQ C
PSU
& MOSFET
SC1547
2.5VSB_STR
& MOSFET
5VSB
SC1547
VCC_S4
& MOSFET
B B
VCC
MOSFET 5VDUAL EZ1084 3VSB LT1084 1.8VSB
VCC12
A A
Title
Reset/Power on Map
Size Document Number Rev
CustomMS-6546 0A
Date: Saturday, September 22, 2001 Sheet 4 of 39
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D D
AGP CK-SKS PROCESSOR RAMBUS CH1 ICH2 PCI Slots
Vcc3_CLK Vccp V_1P8_CMOS_CH1 Vcc3 Vcc3
+12V (3.3V) (3.3V)
(12V) (3.3V) (1.8V MAX.) (1.8V)
V_2P5_CH1 V_3P3_Stby +12V
(12V)
V_AGP_Vddq (2.5V Switched) (3.3V Standby)
(1.5V) DRCG_1 MCH
V_3P3_Stby V_1P8_core Vcc
V_1P8_core (5V)
FB_DRCG1_Vcc3 (3.3V Stanby) (1.8V)
Vcc (3.3V) (1.8V)
C (5V) V_1P8_Stby V_3P3_PCIVAUX C
V_AGP_Vddq RAMBUS CH2 (1.8V Standby) (3.3V Switched)
Vcc3 DRCG_2 (1.5V)
V_1P8_CMOS_CH2 V_3P0_BAT_Vreg
(3.3V) (3.3V Standby)
(Battery Switched)
(1.8V)
FB_DRCG1_Vcc3 Vccp
(3.3V) CNR CONN
(16.5V MAX.) V_2P5_CH2 V_5P0_Stby
FWH (2.5V Switched) (5V Standby) V_3P3_Stby
Audio 9708 (3.3VStandby)
PS2 CONN V_3P3_Stby Vccp
Vcc3
Vcc3 (3.3V Stanby) (1.65V MAX.) +12V
(3.3V)
Vreg_PS2 (3.3V) (12V)
(5V Switched)
Vcc RAMBUS TERM
(5V) Vcc
USB CONN (5V)
SIO
V_5P0_AUD_Analog V_1P8_Vterm_RIMM
Vreg_USB
(5V Analog) (1.8V) V_5P0_Stby
B Vcc3 (5V Switched) B
(3.3V) (5V Standby)
Audio 5880
V_3P3_Stby
(3.3 Standby) Vcc
(5V)
A A
Title
Power Distribution
Size Document Number Rev
CustomMS-6546 0A
Date: Saturday, September 22, 2001 Sheet 5 of 39
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VCCP
VCC3
VCC_SENS 35
R57
10 HA#[3..31] R43 49.9
VID[0..4] 37
VCCP
X_150
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID4
VID3
VID2
VID1
VID0
R56 C35 C32 C36
R72
D D
AD26
AC26
AE25
100 220p 220p 1u
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
U6A
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
49.9
Y1
T5
T4
T2
T1
L2
L3
L6
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
ITP_CLK1
ITP_CLK0
VID4#
VID3#
VID2#
VID1#
VID0#
DBR
VCC_SENSE
VSS_SENSE
10 HDBI#[0..3] HDBI#0 C56 C60 C57
E21 DBI0#
HDBI#1 G25 AA21 R71
HDBI#2 DBI1# GTLREF3 220p 220p 1u
P26 DBI2# GTLREF2 AA6
HDBI#3 V21 F20 100
DBI3# GTLREF1
GTLREF0 F6
AC3 IERR#
V6 AB4 BPM#5
MCERR# BPM5# BPM#5 33
B6 AA5 BPM#4
16,33 FERR# FERR# BPM4# BPM#4 33
Y4 STPCLK# BPM3# Y6
16 STPCLK#
AA3 BINIT# BPM2# AC4
W5 AB5 BPM#1
16,18 HINIT# INIT# BPM1# BPM#1 33
AB2 AC6 BPM#0
RSP# BPM0# BPM#0 33
HREQ#[0..4] 10
H5 H3 HREQ#4
10 HDBSY# DBSY# REQ4# HREQ#3
H2 DRDY# REQ3# J3
10 HDRDY# HREQ#2
10 HTRDY# J6 TRDY# REQ2# J4
K5 HREQ#1
REQ1# HREQ#0
10 HADS# G1 ADS# REQ0# J1
C G4 AD25 R78 C
10 HLOCK# LOCK# TESTHI12
G2 BNR# TESTHI11 A6
10 HBNR#
10 HIT# F3 HIT# TESTHI10 Y3
E3 W4 4.7K R107
10 HITM# HITM# TESTHI9
10 HBPRI# D2 BPRI# TESTHI8 U6
E2 DEFER# TESTHI7 AB22
10 HDEFER# 4.7K
TESTHI6 AA20
C1 AC23 R59
33 TDI_CPU TDI TESTHI5
TESTHI4 AC24
TESTHI3 AC20
D5 AC21 4.7K R49
38 TDO_CPU TDO TESTHI2
TESTHI1 AA2 VCCP
TESTHI0 AD24
F7 4.7K
38 TMS_CPU TMS
BCLK1# AF23 CPUCLK# 8
E6 TRST# BCLK0# AF22 CPUCLK 8
33 TRST#_CPU
D4 F4 HRS#2
38 TCK_CPU TCK RS2# HRS#1
RS1# G5
B3 F1 HRS#0
28,29 VTIN2 THERMDA RS0#
28,29 VAGND C4 THERMDC HRS#[0..2] 10
A2 THERMTRIP# AP1# V5
24,33 THERMTRIP#
AP0# AC1
34 SKTOCC# AF26 SKTOCC# BR0# H6 HBR#0 10,33
B
17,28,33 PROCHOT# C3 PROCHOT# R106 B
B2 IGNNE# COMP1 P1
16 IGNNE#
16 SMI# B5 SMI# COMP0 L24
51RST
16 A20M# C6 A20M
16,29 SLP# AB26 SLP# DP3# L25 R58
A22 RESERVED DP2# K26
A7 RESERVED DP1# K25
AD2 J26 51RST
RESERVED DP0#
AD3 RESERVED
AE21 RESERVED ADSTB1# R5 HADSTB#1 10
AF24 RESERVED ADSTB0# L5 HADSTB#0 10
AF25 RESERVED DSTBP3# W23 HDSTBP#3 10
AB23 PWRGOOD DSTBP2# P23 HDSTBP#2 10
17,33 CPU_PWRGD
10,33 HCPURST# AB25 RESET# DSTBP1# J23 HDSTBP#1 10
HD#63 AA24 F21
D63# DSTBP0# HDSTBP#0 10
HD#62 AA22 W22
D62# DSTBN3# HDSTBN#3 10
HD#61 AA25 R22
D61# DSTBN2# HDSTBN#2 10
HD#60 Y21 K22
D60# DSTBN1# HDSTBN#1 10
HD#59 Y24 E22
D59# DSTBN0# HDSTBN#0 10
HD#58 Y23 E5
D58# LINT1 LINT1 16
HD#57 W25 D1
D57# LINT0 LINT0 16
HD#56 Y26
BSEL0
BSEL1
HD#55 D56#
W26
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D55#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
HD#54 V24
A D54# A
AD6
AD5
M26
M24
M23
M21
G26
G23
G22
U21
U23
U24
U26
R24
R25
R21
N25
N26
N23
N22
H25
H24
D26
H22
D25
D23
C26
H21
C24
C23
D22
C21
V22
V25
P24
P21
K23
E25
E24
B25
B24
A25
A23
B22
B21
T23
T22
T25
T26
F26
F24
F23
L22
L21
J24
J21
SOCKET478 Title
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28