Text preview for : M7V.pdf part of asus M7V asus M7V.pdf
Back to : M7V.pdf | Home
5 4 3 2 1
DDR2 SO-DIMM PCIE SLOT CLOCK
GENERATOR
PAGE 30
CPU FAN + SENSOR
ATI
D D
LVDS
DOTHAN PAGE 5
M24 PAGE 3,4 Power On Sequence
CSP64 PCIE
X16
PAGE 40
PSB
Startup Circuit
PAGE 38,39
PAGE 12
Power Flowchart
LVDS
MCH-M DDR2 DDR2 PAGE 50
PAGE 14
SO-DIMM
CRT
Alviso
PAGE 18,19,20
PAGE 15 PAGE 6,7,8,9,10
C C
DMI interface PCMCIA
TV OUT
PAGE 33
PAGE 15
PCI 33MHz R5C593 1394
PAGE 32
LPC 33MHz PAGE 31,32,33
TPM
ICH6-M CARD READER
PAGE 22
AC97/Azalia PAGE 32
MINI-PCI
802.11 a/b/g
FWH PAGE 26
PAGE 13,14.15
PAGE 22
SATA I/F
B B
AUDIO DJ KEY
PAGE 36 KBC 38857 SATA
HDD
PAGE 34
INSTANT KEY PAGE 21
PAGE 37
PATA
AZALIA CODEC CD ROM
PAGE 23,24,25
PAGE 34
PCIE X1
82570EI LAN
PAGE 27,28,29
PCIE X1
MDC Header USB 2.0 USB 2.0 NEW CARD
PAGE 29 PAGE 22
PAGE 38
A A
Title : BLOCK DIAGRAM
ASUSTeK COMPUTER INC
Engineer: Frank Lu
Size Project Name Rev
Custom M7V 0.95
Date: Monday, November 10, 2003 Sheet 1 of 51
5 4 3 2 1
A B C D E
POWER INTERFACE IMPEDENCE PCB STACK-UP
REVISION LIST SIGNALS TYPE POWER PCB THICKNESS: 1.2 mm
Single-Ended
R0.7 2003/10/13 Only chipset circuit but not including DC to DC power circuit
L1 TOP
R0.8 2003/10/31 Add Intel 82570 chipset circuit and TPM socket PM_PSI# O +VCCP 27.4 OHM WIDTH
L2 GND1
1 R0.9 2003/11/04 Add AZALIA CMI9880 chipset circuit and ALS I/F VR_VID[5:0] O +VCCP TOP/BOT 22 mils 1
IN1/IN3 16 mils L3 IN1
R0.95 2003/11/10 Key Board changed to OKI HMB989-C Matrix VRON O +3.3V
L4 IN2
PM_DPRSLPVR O +3.3V 37.5 OHM WIDTH
L5 VCC
CPU_STP# O +3.3V TOP/BOT 13.5 mils
IN1/IN3 10 mils L6 IN3
RST_BTN# O +3.3V
L7 GND2
CLK_EN# I +3.3V 42 OHM WIDTH
L8 BOT
DELAY_VR_PWRGD I +3.3V TOP/BOT 11 mils PAGE 41
OTP_RESET# I +3.3V IN1/IN3 8.5 mils
SIGNAL IN: VR_VID0 - 5
PM_DPRSLPVR
SHUT_DOWN# I +3.3V 55 OHM WIDTH STP_CPU#
PM_PSI#
BAT_LEARN I +3.3V TOP/BOT 6 mils IMVP_VR_ON
BAT_LLOW#_OC I +3.3V IN1/IN3 5 mils
OUT: DELAY_VR_PWRGD
VR_PWDGD_CK410#
2
BAT1_IN#_OC I +3.3V 75 OHM WIDTH 2
BAT2_IN#_OC I +3.3V TOP/BOT 2.5 mils POWER IN: AC_BAT_SYS
+5VO
CHG_EN_OC I +3.3V IN1/IN3 2 mils +3VO
CHG_LED I +3.3V OUT: +VCORE
SMCLK_BAT1 IO +3.3V Differential PAGE 42
SMDATA_BAT1 IO +3.3V 70 OHM WIDTH/SPACE SIGNAL IN: SUSC#_PWR
VSUS_ON
SMCLK_BAT2 IO +3.3V TOP/BOT 8 mils/ 4 mils
SMDATA_BAT2 IO +3.3V IN1/IN3 8 mils/ 3.5 mils
POWER IN: AC_BAT_SYS
SUSB# O +3.3V 90 OHM WIDTH/SPACE
SUSC# O +3.3V TOP/BOT 5 mils/ 5 mils OUT: +12VO
+3VO
1.8V_PWRGD I +3.3V IN1/IN3 5 mils/ 5 mils +5VO
1.5VS_PWRGD I +3.3V 100 OHM WIDTH/SPACE PAGE 43
3 VSUS_ON O +3.3V TOP/BOT 4 mils/ 6 mils SIGNAL IN: SUSB#_PWR 3
SUSC#_PWR
ACIN_OC I +3.3V IN1/IN3 4.25 mils/ 5.75 mils
ACIN# I AC_BAT_SYS POWER IN: AC_BAT_SYS
+3VO
+3VA PWR +3.3V
+5VA PWR +5V
PCI INTERFACE OUT: +1.8V
+1.5V
+2.5V
+VCC_GMCH_CORE
+5VLCM PWR +5VLCM PCI_REQ# +5VALWAYS
+3VALWAYS
A/D_DOCK_IN PWR DC
CB&1394 PCI_REQ#1 PAGE 44
AC_BAT_SYS PWR DC
MINIPCI PCI_REQ#3 SIGNAL IN: SUSB#_PWR
OUT: VCC_MCH_VRPWRGD
POWER PLANE IDSEL IMVP_VR_ON
POWER VOLTAGE CURRENT POWER IN: +3VA
CB&1394 PCI_AD17 +3V
4 +VCORE 0.7 - 1.77V 27A +1.8V
4
MINIPCI PCI_AD19 +VCC_GMCH_CORE
+VCCP 1.05 - 1.2V 3.95A
+VCC_GMCH 1.05V 4.12A OUT: +0.9VS
+1.5VA
+0.9VS 1.25V 0.5A
+1.5VS 1.5V 4.33A
PCIE Device +VCCP
+1.5V 1.5V 300 mA PEG
+1.5VSUS 1.5V 270 mA
ATI M24
+1.8V 1.8V 6.68A
+2.5VS 2.5V 0.3 A
+3VS 3.3V 1.732A PCIE Giga NIC
+3V 3.3V 1.515A
Intel 82570EI
5
+3VSUS 3.3V 390 mA 5
+5VS 5V 4.1A
+5V 5V 0.5A Title : REVISION LIST
+5VSUS 5V 0.5A Engineer: Frank Lu
ASUSTeK COMPUTER INC
+12V 12V 0.25A Size Project Name Rev
+12VS 12V 0.25A Custom M7V 0.95
Date: Monday, November 10, 2003 Sheet 2 of 51
A B C D E
5 4 3 2 1
+VCCP
1
H_D#[0..63] 6
R1
6 H_A#[16..3]
U1B 56Ohm
H_A#16 AA2 N2 U1A
A[16]# ADS# H_ADS# 6
H_A#15 Y3 A10 1 T1 TPC28 H_D#15 C25 Y25 H_D#47
2
H_A#14 A[15]# PRDY# H_D#14 D[15]# D[47]# H_D#46
AA3 A[14]# PREQ# B10 E23 D[14]# D[46]# AA26
H_A#13 U1 H_D#13 B23 Y23 H_D#45
H_A#12 A[13]# H_D#12 D[13]# D[45]# H_D#44
Y1 A[12]# BNR# L1 H_BNR# 6 C26 D[12]# D[44]# V26
H_A#11 Y4 J3 H_D#11 E24 U25 H_D#43
A[11]# BPRI# H_BPRI# 6 D[11]# D[43]#
ADDRESS GROUP 0
D H_A#10 W2 H_D#10 D24 V24 H_D#42 D
H_A#9 A[10]# H_D#9 D[10]# D[42]# H_D#41
DATA GROUP 0
T4 B24 U26
2
H_A#8 A[9]# T3 TPC28 H_D#8 D[9]# D[41]# H_D#40
W1 A[8]# DBR# A7 1 C20 D[8]# D[40]# AA23
DATA GROUP
H_A#7 V2 H_D#7 B20 R23 H_D#39
H_A#6 A[7]# H_D#6 D[7]# D[39]# H_D#38
R3 A[6]# A21 D[6]# D[38]# R26
H_A#5 V3 H_D#5 B26 R24 H_D#37
H_A#4 A[5]# H_D#4 D[5]# D[37]# H_D#36
U4 A[4]# DEFER# L4 H_DEFER# 6 A24 D[4]# D[36]# V23
H_A#3 P4 H2 H_D#3 B21 U23 H_D#35
A[3]# DRDY# H_DRDY# 6 D[3]# D[35]#
U3 M2 H_D#2 A22 T25 H_D#34
6 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 6 D[2]# D[34]#
H_REQ#4 T1 H_D#1 A25 AA24 H_D#33
H_REQ#3 REQ[4]# H_D#0 D[1]# D[33]# H_D#32
P1 REQ[3]# A19 D[0]# D[32]# Y26
H_REQ#2 T2 D25 T24
REQ[2]# +VCCP 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
H_REQ#1 P3 C23 W25
REQ[1]# 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#0 R2 C22 W24
REQ[0]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
BR0# N4 H_BR0# 6
CONTROL
H_D#31 K25 AF26 H_D#63
6 H_REQ#[4..0] D[31]# D[63]#
H_D#30 N25 AF22 H_D#62
H_IERR# R2 D[30]# D[62]#
6 H_A#[31..17] IERR# A4 1 2 56Ohm H_D#29 H26 D[29]# D[61]# AF25 H_D#61
H_D#28 M25 AD21 H_D#60
H_A#31 H_D#27 D[28]# D[60]# H_D#59
AF1 A[31]# N24 D[27]# D[59]# AE21
H_A#30 AE1 B5 H_D#26 L26 AF20 H_D#58
A[30]# INIT# H_INIT# 13 D[26]# D[58]#
3
H_A#29 H_D#25 H_D#57
DATA GROUP 1
AF3 A[29]# J25 D[25]# D[57]# AD24
H_A#28 AD6 H_D#24 M23 AF23 H_D#56
DATA GROUP
A[28]# D[24]# D[56]#
ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#23 J23 AE22 H_D#55
A[27]# LOCK# H_LOCK# 6 D[23]# D[55]#
H_A#26 AD5 H_D#22 G24 AD23 H_D#54
H_A#25 A[26]# H_D#21 D[22]# D[54]# H_D#53
AC6 A[25]# F25 D[21]# D[53]# AC25
H_A#24 AB4 H_D#20 H24 AC22 H_D#52
H_A#23 A[24]# H_D#19 D[20]# D[52]# H_D#51
AD2 A[23]# M26 D[19]# D[51]# AC20
C H_A#22 AE4 H_D#18 L23 AB24 H_D#50 C
H_A#21 A[22]# H_D#17 D[18]# D[50]# H_D#49
AD3 A[21]# RESET# B11 H_CPURST# 6 G25 D[17]# D[49]# AC23
H_A#20 AC3 L2 H_RS#2 H_D#16 H23 AB25 H_D#48
H_A#19 A[20]# RS[2]# H_RS#1 D[16]# D[48]#
AC7 A[19]# RS[1]# K1 6 H_DINV#1 J26 DINV[1]# DINV[3]# AD20 H_DINV#3 6
H_A#18 AC4 H1 H_RS#0 K24 AE24
A[18]# RS[0]# 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
H_A#17 AF4 L24 AE25
A[17]# H_RS#[0..2] 6 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
6 H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# 6
SOCKET479P
HIT# K3 H_HIT# 6
6 H_DPWR# C19 DPWR# HITM# K4 H_HITM# 6
SOCKET479P
U1C
30 CLK_CPU_BCLK B15 BCLK[0]
B14
HOSTCLK
30 CLK_CPU_BCLK# R3 BCLK[1]
2 49.9Ohm H_COMP3 R4 54.9Ohm
R5
1
1 2 49.9Ohm
A16
A15
ITP_CLK[0] COMP[3] AB1
AB2 H_COMP2 R6
1
1
2
2 27.4Ohm NO STUFF
ITP_CLK[1] COMP[2] H_COMP1 R7 54.9Ohm +VCCA_PROC
COMP[1] P26 1 2 Q102
C2 P25 H_COMP0 R8 1 2 27.4Ohm R19 1 2 0Ohm
13 H_A20M# A20M# COMP[0] +1.5VS
D3 / SI2304DS
13 H_FERR# FERR# GND
LEGACY CPU
GND 13 H_IGNNE# A3 IGNNE#
B7 C9 R12 1 2 0Ohm 3 2
2 S
13 H_DPSLP# +1.8V +VCCA_PROC_IN
D
DPSLP# BPM[3]#
A6 A9
3
6,13 H_CPUSLP# SLP# BPM[2]# +VCCP
13 H_INTR D1 LINT0 BPM[1]# B8
G
+5V
1
D4 C8 C6
1 1
13 H_NMI LINT1 BPM[0]# +1.8V_PROC R142
B 13 H_SMI# B4 SMI# 1 B
C6 1 2 0.01U
13 H_STPCLK# STPCLK# R11
2
1
1
2
E4 AC1 C1 C2 100KOhm
13 H_PWRGD PWRGOOD GTLREF[3]