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5 4 3 2 1
Big Bear 2A (AS 18") Block Diagram
Project code: 91.4AJ01.001
PCB P/N : 48.4AJ01.001
REVISION : 08208-1
DDR2 667/800MHz PCB STACKUP SYSTEM DC/DC
AMD Giffin CPU TPS51125 47
D 667/800 MHz
8,9 G792 TOP
INPUTS OUTPUTS
D
S1G2 (35W) 25 VCC
DCBATOUT
5V_S5(7A)
DDR2 667/800MHz
638-Pin uFCPGA638
4,5,6,7
S
3D3V_S5(7A)
667/800 MHz SYSTEM DC/DC
8,9 S TPS51124 48
CRT
18 GND INPUTS OUTPUTS
OUT
1D1V_S0(8A)
IN
16X16 BOTTOM DCBATOUT
CLK GEN. LCD 1D2V_S0(5A)
16
ICS ICS9LPRS480 SYSTEM DC/DC
3 North Bridge HDMI TPS51117 49
AMD RS780M 19 INPUTS OUTPUTS
Line In CPU I/F LVDS, CRT I/F
DCBATOUT 1D8V_S3(10A)
INTEGRATED GRAHPICS PCIex16
40 Codec AZALIA RT9026PFP 50
VGA Borad DDR_VREF_S3
C ALC888S 35 1D8V_S3 C
MIC In 38 11,12,13 0D9V_S3(1A)
40 RT9166 50
A-Link
LAN
Giga LAN TXFM RJ45 3D3V_S0 2D5V_S0
Line Out(With-SPDIF) 34 34 (300mA)
4X4 BCM5764MKMLG 33
OP AMP G957 50
40
G1412R 39 New card PWR SW 3D3V_S0 1D5V_S0(1A)
36 W83L35136
Front.SPKR South Bridge G9161 50
AMD SB700 PCIex1
OP AMP Mini Card 3D3V_S5 1D2V_S5
40 Kedron a/b/g/n 37 (400mA)
G1454R 39 USB 2.0 12 ports
USB 1.1 2 ports
Mini Card CHARGER
TV tuner
MAX8731A 51
ETHERNET (10/100/1000Mb) 37
SUBWOOFER High Definition Audio INPUTS OUTPUTS
ATA 66/100 CardReader SD/SD IO/MMC/MMC
B
40 OP AMP USB CHG_PWR
B
G1442R 39 ACPI 1.1 RTS5158E /MS/MS PRO/XD
7 in 1 18V 6.0A
LPC I/F
32 32 DCBATOUT
UP+5V
PCI/PCI BRIDGE 5V 100mA
20,21,22,23,24 LPC BUS
CPU DC/DC
BIOS ISL6265HR 46
USB Winbond INPUTS OUTPUTS
W25X80
SATA KBC 42 LPC VCC_CORE_S0_0
Winbond 0~1.55V 18A
Mini USB Camera DEBUG
MODEM WPC773L Launch CONN.42 VCC_CORE_S0_1
Blue Tooth 28 16 41 Button
DCBATOUT
0~1.55V 18A
RJ11 MDC Card 15
29 VDDNB
Finger USB 0~1.55V 18A
HDD SATA I Printer 31 4 Port 30 Touch INT. CIR
A 27 Pad 41 KB 41 42 A
ODD SATA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
26
Title
HDD SATA II
BLOCK DIAGRAM
Size Document Number Rev
A3 SC
27 Big Bear 2A
Date: Monday, October 27, 2008 Sheet 1 of 55
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HISTORY
Size Document Number Rev
A3 Big Bear 2A SA
Date: Monday, October 27, 2008 Sheet 2 of 55
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
0R0603-PAD 3D3V_S0
1 2 R139
R138 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
1
C343 C340 C344 C341 C354 C357 C359 C355 C360
SC4D7U6D3V3KX-GP
-1_1014 Due to PLL issue on current clock chip, the SBlink clock
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C345 C348
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY DY DY
2
2
2
2
2
2
2
2
2
3000mA.80ohm Future clock chip revision will fix this.
2
2
D D
Clock chip has internal serial terminations
3D3V_S0
-1_1014 for differencial pairs, external resistors are
0R0603-PAD reserved for debug purpose.
1 2
R150
1D1V_S0 DY 1D1V_CLK_VDDIO
R151 C351
1 2 R140 SC33P50V2JN-3GP
0R3-0-U-GP 1 DY 2 2 1
1
1
1
1
1
1
1
C361 C362 C347 C352 C356 C358 C342 3D3V_CLK_VDD X2
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP X-14D31818MHZ-4-GP
DY DY U13 82.30005.A41
2
2
2
2
2
2
2
1D1V_CLK_VDDIO 2ND = 82.30005.891
26 61 GEN_XTAL_IN C346
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 2 1
CL=20pF