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Schematic Diagrams
Appendix B:Schematic Diagrams
This appendix has circuit diagrams of the M540SE/M550SE notebook's PCB's. The following table indicates where to
find the appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page Table B - 1
Schematic
System Block Diagram - Page B - 2 VT8237 2/3 - Page B - 15 +1.8V, +VTT_MEM - Page B - 28
Diagrams
PROCESSOR 1/2 - Page B - 3 VT8237 3/3 - Page B - 16 VCORE - Page B - 29
B.Schematic Diagrams
PROCESSOR 2/2 - Page B - 4 MINI PCI, MINI Card, USB2.0*2, FP - Page B - 17 +1.05VS, 1.5V, 1.5VS - Page B - 30
VN896 1/4 - Page B - 5 SATA HDD, CD-ROM, H8 BEEP, CCD - Page B - 18 +VDD3, +VDD5 - Page B - 31
VN896 2/4 - Page B - 6 LAN PHY - Page B - 19 D/D BD (CRT, INVERTER, CCD, RJ-11) - Page B - 32
VN896 3/4 - Page B - 7 LPC ROM, TOUCH PAD, LED - Page B - 20 D/D BD (CHARGER, DC IN) - Page B - 33
VN896 4/4 - Page B - 8 H8-2111 - Page B - 21 AUDIO BD (PHONE JACK, USB, RJ-11) - Page B - 34
DDR2-1 - Page B - 9 MDC, USB BT, PWRGD, DDB CON - Page B - 22 HOT KEY BD (HOT KEY, LED, LID) - Page B - 35
DDR2-2 - Page B - 10 Audio VT1708A/ALC883 - Page B - 23 LED BOARD - Page B - 36
Version Note
CLOCK GENERATOR - Page B - 11 AUDIO AMP, USB2.0*2 - Page B - 24 CLICK BOARD - Page B - 37
The schematic dia-
grams in this chapter
PANEL, FAN - Page B - 12 PCI ENE MR510 - Page B - 25 RJ-45 BOARD - Page B - 38
are based upon ver-
VIA LVDS VT-1634AL - Page B - 13 NEW CARD, 3-IN-1 SOCKET - Page B - 26 USB DONGLE BOARD - Page B - 39 sion 6-71-M5E50-
D02A. If your main-
VT8237 1/3 - Page B - 14 5V, 3V, 5VS, 3VS, 2.5V, 2.5VS - Page B - 27 FINGERPRINT BOARD - Page B - 40 board (or other boards)
are a later version,
please check with the
Service Center for up-
dated diagrams (if re-
quired).
B - 1
Schematic Diagrams
System Block Diagram
CLEVO M540SE/M550SE System Block Diagram
D/D BOARD 1.+3V,+5V ,+2.5V
1.CHARGER,DC JACK
2.INVERTER 2.,+3VS,+5VS ,+2.5VS
3.CRT,CCD
4.M550S SPK MAIN CLOCK MEMORY TERMINATIONS
CPU 1.+VTT_MEM,+1.8V
ICS953009AF
PHONE JACK&USB BOARD YONAH/MEROM
1.AUDIO PHONE JACK PROCESSOR DDR2 SDRAM SOCKET DDR VR 1.+VCORE
2.USB CONNECTOR,RJ11
CLOCK
BUFFER 479 uFCPGA 1.+1.05VS,+1.5V,1.5VS
HOT KEY BOARD&POWER SWITCH ICS9P956AF SO-DIMM0 SO-DIMM1 (Option)
1.POWER BOTTON
B.Schematic Diagrams
2.INDICATOR LED FSB 1.VDD3,VDD5
3.LID SWITCH CRT
ON BOARD AUDIO BOARD
Sheet 1 of 39 LED BOARD(FOR M550SE) NB BULE BLACK PINK GREEN
System Block 1.INDICATOR LED
LCD CONN VT1634A
VN896 667MHz
LINE SPDIF MIC HP
Diagram CLICK BOARD(FOR M550SE)
(LVDS) LVDS IN OUT
IN
OUT
HSBGA-951 MDC
1.T/P SWITCH BOTTOM MODULE
(Option)
RJ-45 BOARD CODEC AUDIO INT.
VLINK 533MB/sec VIA 1708A AMP. SPK
MDC CONN. APA2020A
PCI-E SM BUS
USB2.0 AZALIA
SB
CCD PHONE JACK VT8237A PCI BUS 33MHz
USB 5 BOARD
MII
USB 0 HSBGA-541
Mini IDE PHY CARD READER
PCIE BT USB 3 SATA HDD
VT6103 ENE
LPC LPC
RJ-11 MR510
USB 6 USB 1
(Option) USB 2 Mini PCI
KBC SYSTEM SOCKET
H8/2111
BIOS
NEW CARD TOUCH
PAD 3 IN 1
USB 7 Debug ? RJ-45 CARD
SM BUS (35+25 Pin Conn.? ? ) READER
+VDD +*V +*VS
CPU FAN
TEMP SMART FULL ON ON ON
SENSOR BATTERY ON
ADM1032
S3 ON ON OFF
CD-ROM/CD-RW/
KBC CONN DVD-ROM/DVD+-RW S4 ON OFF OFF
B-2
Schematic Diagrams
PROCESSOR 1/2
JSKT1A JSKT1B
4 H_A#[31:3] 4 H_D #[63:0] H_D#[63:0] 4
H_A#3 J4 H1 H_D#0 E22 AA23 H_D#32
A[3]# ADS# H_ADS# 4 D[0]# D[32]#
H_A#4 L4 E2 H_D#1 F 24 AB24 H_D#33
A[4]# BNR # H_BNR# 4 D[1]# D[33]#
H_A#5 M3 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 4 D[2]# D[34]#
H_A#6 K5 H_D#3 H22 V26 H_D#35
A[6]# D[3]# D[35]#
DATA GRP 0
H_A#7 M1 H5 H_D#4 F 23 W25 H_D#36
DATA GRP 2
A[7]# DEF ER # H_DEF ER# 4 D[4]# D[36]#
ADDR GROUP 0
H_A#8 N2 F 21 H_D#5 G25 U23 H_D#37
A[8]# DRDY # H_DRDY # 4 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY # H_DBSY # 4 D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U22 H_D#39
CONTROL
H_A#11 P5 A[10]# F1 H_D#8 K24 D[7]# D[39]# AB25 H_D#40
A[11]# BR0# H_BREQ#0 4 D[8]# D[40]#
H_A#12 P2 H_D#9 G24 W22 H_D#41
H_A#13 L1 A[12]# D20 H_IERR# H_D#10 J 24 D[9]# D[41]# Y 23 H_D#42
H_A#14 P4 A[13]# IERR # B3 H_INIT# H_D#11 J 23 D[10 D[42]# AA26 H_D#43
A[14]# INIT# H_IN IT# 15 D[11]# D[43]#
H_A#15 P1 H_D#12 H26 Y 26 H_D#44 H_DIN V#[3:0]
A[15]# D[12]# D[44]# 4 H _DIN V#[3:0]
H_A#16 R1 H4 H_D#13 F 26 Y 22 H_D#45
A[16]# LOCK# H_LOCK# 4 D[13]# D[45]#
4 H_ADSTB#0
4 H_REQ#[4:0]
H_REQ#0
H_REQ#1
L2
K3
H2
ADSTB[0]#
REQ[0]#
RESET#
R S[0]#
B1
F3
F4
H_CPURST#
H_CPUR ST# 4
H_RS#0 4 4 H_DSTBN#0
H_D#14
H_D#15
K22
H25
H23
G22
D[14]#
D[15]#
DSTBN[0]#
D[46]#
D[47]#
DSTBN[2]#
AC26
AA24
W24
Y 25
H_D#46
H_D#47
H_DSTBN#2 4
Sheet 2 of 39
REQ[1]# R S[1]# H_RS#1 4 4 H_D STBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 4
H_REQ#2
H_REQ#3
H_REQ#4
K2
J3
L5
REQ[2]#
REQ[3]#
REQ[4]#
R S[2]#
TRDY #
G3
G2
H_RS#2 4
H_TRDY # 4
4 H_D INV#0
4 H_D #[63:0]
J 26
DINV[0]# DINV[2]#
V23
H_DINV#2 4
H_D#[63:0] 4
+3VS
PROCESSOR 1/2
G6 H_D#16 N22 AC22 H_D#48
4 H_A#[31:3] HI T# H_HIT# 4 D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AC23 H_D#49
A[17]# HITM# H_HITM# 4 D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AB22 H_D#50
H_A#19 R3 A[18]# AD4 H_BPM0# H_D#19 R23 D[18]# D[50]# AA21 H_D#51 R 345
A[19]# BPM[0]# D[19]# D[51]#
DATA GRP 1
H_A#20 W6 AD3 H_BPM1# H_D#20 L25 AB21 H_D#52
DATA GRP 3
H_A#21 U4 A[20]# BPM[1]# AD1 H_BPM2# H_D#21 L22 D[20]# D[52]# AC25 H_D#53 10K_06
XDP/ITP SIGNALS
A[21]# BPM[2]# D[21]# D[53]# Q49
B.Schematic Diagrams
H_A#22 Y5 AC4 H_BPM3# Layout Note: H_D#22 L23 AD20 H_D#54 2N3904
H_A#23 U2 A[22]# BPM[3]# AC2 H_PR DY # H_D#23 M23 D[22]# D[54]# AE22 H_D#55 F ER R# E C
A[23]# PRDY # COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms D[23]# D[55]# H_F ERR# 15
H_A#24 R4 AC1 H_PR EQ# H_D#24 P25 AF 23 H_D#56
H_A#25 T5 A[24]# PREQ# AC5 H_TCK H_D#25 P22 D[24]# D[56]# AD24 H_D#57
H_A#26 T3 A[25]# TCK AA6 H_TDI
COMP1, COMP3: 0.5" Max, Zo=55 Ohms H_D#26 P23 D[25]# D[57]# AE21 H_D#58 +1.05VS
H_A#27 W3 A[26]# TDI AB3 H_TDO Best estimate is 18 mils wide trace H_D#27 T24 D[26]# D[58]# AD21 H_D#59 Z 0223
B
H_A#28 W5 A[27]# TDO AB5 H_TMS +1.05VS H_D#28 R24 D[27]# D[59]# AE25 H_D#60 R346 10K_04
H_A#29 Y4 A[28]# TMS AB6 H_TRST# for outer layers and 14 mils wide H_D#29 L26 D[28]# D[60]# AF 25 H_D#61
H_A#30 W2 A[29]# TR ST# C20 ITP_DBRST# H_D#30 T25 D[29]# D[61]# AF 22 H_D#62
A[30]# DBR # trace if on internal layers. D[30]# D[62]#
H_A#31 Y1 H_D#31 N24 AF 26 H_D#63
V4 A[31]# D21 H_PR OCHOT# M24 D[31]# D[63]# AD23
4 H_ADSTB#1 ADSTB[1]# PR OCHOT 4 H_D STBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 4
A24 H_THERMDA R351 N25 AE24
H_A20M# TH ERMDA 4 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 4
A6 A25 H_THERMDC *680_04 M26 AC20
THERM
15 H_A20M# F ERR # A20M# THERMDC 4 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 4
A5
H_IGNNE# C4 F ERR# C7 PM_THRMTRIP# AD26 R26 COMP0
15 H_IGN NE# IGNNE# TH ER MTRIP# PM_THRMTRI P# 30 GTLREF COMP[0]
No stub on H_STPCLK# test MISC COMP[1]
U26 COMP1
H_STPCLK# D5 U1 COMP2
point 15 H_STPCLK# H_INTR STPCLK# Z0220 C26 COMP[2] COMP3
C6 R386 *1K_04 V1
15 H_IN TR
H CLK
H_NMI B4 LINT0 A22 TEST1 COMP[3]
15 H_NMI H_SMI # LINT1 BC LK[0] CPU _CLK+ 10
A3 A21 R385 51_1%_06 Z0221 D25 E5 H_DPRSLPVR#
15 H_SMI# SMI# BC LK[1] CPU _CLK- 10 TEST2 DPRSTP# H_DPSLP#
B5
Z 0201 DPSLP# H_DPSLP# 15
AA1 D24
Z 0202 RSVD[ 01]# DPW R# H_DPWR# 4
AA4 T22 Z 0212 T31 B22 D6 H_PWRGD
Z 0203 RSVD[ 02]# RSVD[12]# 10 CPU_BSEL0 BSEL[0] PW RGOOD H_CPUSLP# H_PWRGD 21
AB2 B23 D7
Z 0204 RSVD[ 03]# 10 CPU_BSEL1 Z0222 C21 BSEL[1] SLP# H_PSI# H_CPUSLP# 4,15
AA3 AE6
RESERVED
Z 0205 M4 RSVD[ 04]# D2 Z 0213 BSEL[2] PSI#
Z 0206 N5 RSVD[ 05]# RSVD[13]# F6 Z 0214
RSVD[ 06]# RSVD[14]# Layout Note:
Z 0207 T2 D3 Z 0215 R391 *0_06 PZ 47913-2741-01
Z 0208 V3 RSVD[ 07]# RSVD[15]# C1 Z 0230 H_ADSTB0# 0.5" max,
RSVD[ 08]# RSVD[16]# H _ADSTB0# 4
Z 0209 B2
RSVD[ 09]# RSVD[17]#
AF1 Z 0216 Zo= 55 Ohms
Z 0210 C3 D22 Z 0217
RSVD[ 10]# RSVD[18]# C23 Z 0218 CPU_GTLR EF R379 1K_1%_06
Z 0211 RSVD[19]# Z 0219 +1.05VS
B25 C24
+1.05VS RSVD[ 11]# RSVD[20]#
PZ 47913-2741-01 C473 C472 C 471 R380
R325 54.9_1%_06H_PREQ#
R324 54.9_1%_06H_PRDY # 1u_10V_06
0.1u/16V_04 0.01u/25V_04 2K_1%_06
R22 54.9_1%_06H_TMS
R21 75_1%_06 H_TDO COMP0
R19 54.9_1%_06H_TDI COMP1
R58 75_1%_06 H_PROCHOT# COMP2
R59 51_1%_06 H_IERR# COMP3
R350 51_1%_04 FERR# R328
R 329 R387 R388
R352 150_04 H_A20M#
R344 150_04 H_IGNNE# 54.9_1%_06 54.9_1%_06
R340 150_04 H_INIT# 27.4_1%_06 27.4_1%_06
R349 150_04 H_INTR
R339 150_04 H_STPCLK# Q4
R347 150_04 H_NMI