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A B C D E
Biwa Block Diagram Project code: 91.4H001.001
PCB P/N : 55.4H001.XXX
REVISION : 06237-2(GCE, Hannstar)
Mobile CPU
4 CLK GEN. Merom 479 4
-2-0226
ICS 9LPR502
G792
(RTM875T-605) 3
2G/2.33G 20
PCB STACKUP
2.0G : B0, QLYV
2.2G : B0, QLFS
4, 5 TOP
CPU DC/DC
HOST BUS [email protected] VCC MAX8770 36
DDR2 533/667MHz
SVIDEO/COMP
TVOUT 15
S INPUTS OUTPUTS
533/667 MHz Crestline S VCC_CORE_S0
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AGTL+ CPU I/F LVDS 14" WXGA DCBATOUT
12,13 GND 0~1.3V
DDR Memory I/F LCD 14 47A
INTEGRATED GRAHPICS BOTTOM
DDR2 533/667MHz LVDS, CRT I/F
RGB CRT
CRT 15 SYSTEM DC/DC
ISL6236 37
533/667 MHz 71.CREST.M02, B0, QN12 6,7,8,9,10,11
12,13 X4 DMI INPUTS OUTPUTS
3 C-Link0 3
400M Byte/s PCMCIA I/F 5V_S5(5A)
PCMCIA DCBATOUT 3D3V_S5(5A)
Line In 5V_AUX_S5
TI 7412 PWR SW SLOT
30 Support
Codec AZALIA CardBus TPS2211 SYSTEM DC/DC
ALC268 ICH8M PCI BUS
27 TypeII
27
MAX8717 38
29 1394 1394 INPUTS OUTPUTS
6 PCIe ports
Mic In PCI/PCI BRIDGE CardReader CONN 26 1D05V_S0(13A)
25,26
MS/MS Pro/xD/ DCBATOUT
30 ACPI 1.1 1D8V_S3(10A)
MMC/SD/SDIO
3 SATA 6 in 1 G971 39
INT.MIC 1 PATA 66/100
27
1D8V_S3 1D5V_S0
10 USB 2.0/1.1 ports (4A)
30 OP AMP ETHERNET (10/100/1000MbE)
LAN
Giga LAN TXFM RJ45 APL5913 39
APA2031 High Definition Audio
24 24
30 BCM5787MKMLG 23 1D8V_S3 1D25V_S0
INT.SPKR LPC I/F (1.5A)
2 Serial Peripheral I/F PWR SW G2997F6U 39 2
Matrix Storage Technology(DO)
New card
28 P2231NFC
28 DDR_VREF_S0
30
G1412 30 Active Managemnet Technology(DO) PCIex1 Mini Card 1D8V_S3
(1.2A)
DDR_VREF_S3
Line Out Kedron a/b/g/n 28
G909 34
(No-SPDIF) C Link1
5V_AUX_S5 3D3V_AUX_S5
MODEM 71.0ICH8.A0U, B1, QN23 (100mA)
16,17,18,19
LPC BUS
RJ11
24 MDC Card MAXIM CHARGER
22 ISL6255 40
SATA
PATA
Super I/O INPUTS OUTPUTS
Winbond
KBC
Winbond SPI I/F 33
LPC
BIOS DEBUG CHG_PWR
PC87381 WPC8763L W25X80-VSSI-G
HDD USB22 CCD14
33 31 CONN. 33 DCBATOUT
19V 4.0A
21 4 PORT UP+5V
5V 100mA
1
MINI USB 22 Finger FIR
Touch INT. 55.4H001.S03G
Digitally signed by dd 1
CDROM Blue-tooth PT 32 Pad32 KB 32
DN: cn=dd, o=dd, ou=dd,
Wistron Corporation
21 22 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
[email protected],
Taipei Hsien 221, Taiwan, R.O.C.
c=US
Title
BLOCK DIAGRAM
Size
A3 Date: 2009.12.19 05:15:24
Document Number
Biwa -2
Rev
+07'00'
Date: Thursday, March 01, 2007 Sheet 1 of 42
A B C D E
ICH8M Functional Strap Definitions
ICH8-M EDS 21762 2.0V1 page 16
ICH8M Integrated Pull-up Crestline Strapping Signals and
Signal Usage/When Sampled Comment and Pull-down Resistors Configuration Crestline EDS 20954
page 7
1.0
ICH8-M EDS 21762 2.0V1
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: SIGNAL Resistor Type/Value CFG[2:0] FSB Frequency Select 001 = FSB533
offset 224h) HDA_BIT_CLK PULL-DOWN 20K 011 = FSB667
010 = FSB800
HDA_RST# NONE others = Reserved
4 HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h) CFG[4:3] Reserved
4
Rising Edge of PWROK. HDA_SDIN[3:0] PULL-DOWN 20K
GNT2# PCIE config2 bit0, This signal has a weak internal pull-up. HDA_SDOUT PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) 1 = DMI x4 (Default)
HDA_SYNC PULL-DOWN 20K CFG[8:6] Reserved
GPIO20 Reserved This signal should not be pulled high.
GNT[3:0] PULL-UP 20K 0 = Normal mode
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. Low Power PCI Express 1 = Low Power mode (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop GPIO[20] PULL-DOWN 20K (?)
and mobile. 0 = Reverse Lanes,15->0,14->1 ect..
LDA[3:0]#/FHW[3:0]# PULL-UP 20K CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
Lane Reversal Numbered in order
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for LAN_RXD[2:0] PULL-UP 10K
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the LDRQ[0] PULL-UP 20K CFG[11:10] Reserved
Top-Swap bit until the system is rebooted XOR/ALL Z test 00 = Reserved
LDRQ[1]/GPIO23 PULL-UP 20K
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without GNT3# being pulled down. CFG[13:12] straps 01 = XOR mode enabled
PME# PULL-UP 20K 10 = All Z mode enabled
GNT0#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit 11 = Normal Operation (Default)
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). PWRBTN# PULL-UP 20K
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. CFG[15:14] Reserved Reserved
SATALED# PULL-UP 15K
Integrated VccSus1_05, Enables integrated VccSus1_05, VccSus1_5 and CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
INTVRMEN VccSus1_5 and VccCL1_5 VccCL1_5 VRM's when sampled high SPI_CS1# PULL-UP 20K 1 = Dynamic ODT Enabled (Default)
VRM Enable/Disable.
Always sampled. SPI_CLK PULL-UP 20K
CFG[18:17] Reserved
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05 and VccCL1_05 VRM's
SPI_MOSI PULL-UP 20K
0 = Normal operation (Default):lane 3
LAN100_SLP and VccCL1_05 VRM when sampled high SPI_MISO PULL-UP 20K CFG19 DMI Lane Reversal Numbered in order
Enable/Disable.
Always sampled. TACH_[3:0] PULL-UP 20K (?) 1 =Reverse Lane,4->0,3->1 ect...
SPKR PULL-DOWN 20K 0 = Only SDVO or PCIE x1 is
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 CFG20 SDVO/PCIE operational (Default)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) TP[3] PULL-UP 20K Concurrent 1 =SDVO and PCIE x1 are operating
of PWROK. simultaneously via the PEG port
USB[9:0][P,N] PULL-DOWN 15K
SPKR No Reboot. If sampled high, the system is strapped to the SDVOCRTL SDVO Present 0 = No SDVO Card present (Default)
Rising Edge of PWROK. "No Reboot" mode(ICH8 will disable the TCO Timer CL_RST# PULL-UP 13K _DATA
system reboot feature). The status is readable 1= SDVO Card present
via the NO REBOOT bit.
NOTE: All strap signals are sampled with respect to the leading
TP3 XOR Chain Entrance. This signal should not be pull low unless using edge of the Crestline GMCH PWORK in signal.
Rising Edge of PWROK. XOR Chain testing.
GPIO33/ Flash Descriptor This signal has a weak internal pull-up.
History
HDA_DOCK Security Override Strap Sampled low:the Flash Descriptor Security will be
_EN# Rising Edge of PWROK overridden. If high,the security measures will be 2007/02/16
in effect.This should only be used in manufacturing 1.Page 33: Add SIO 87381 for FIR Issue.
environments. 2.Page 31, change KBC from 8768L to 8763L.
3.Page 33, del U33(LPC golden Finger).
4.Page 24/32, change ERC1/ERC2 due to 77.61021.02L is Obsoleted Part !
5.Page 37, del TC22/TC19.
2 6.Page 38, del TC1/TC4. 2
===========================================================
ICH8M IDE Integrated Series 2007/02/09
1.Page 14:Modify "Q14" "BTBTN1" "WLBTN1" symbol.
2.Page 36, 37, 38: Replace 0ohm with 0ohm pad.
Termination Resistors ===========================================================
2007/02/08a
1.Page 14:Modify R428 to"FRONT_PWRLED#_1"and RN58 pin7 to"STBY_LED#_2"due to LED brightness issue.
DD[15:0], DIOW#, DIOR#, DREQ, 2.Page 38:Replace "TC26" with "77.C1561.01L".
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#, ===========================================================
2007/02/08
DCS3#, IDEIRQ 1.Page 10:Replace "R244" with "0603-PAD".
2.Page 36:Replace open power gap with close power gap.
page 17
USB Table 3.Page 38:Add capacitor "TC26" for acoustic noise
===========================================================
PCI Routing USB
IDSEL INT REQ GNT Pair Device
G:CARDBUS 0 0 0 USB1
TI7412 AD22 B:1394
F:Flash Media 1 USB2
G:SD Host 2 USB3
3 USB4
1 55.4H001.S03G
1
4 MINIC1
PCIE Routing 5 BT Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE1 LAN BCM5787M 6 CCD Taipei Hsien 221, Taiwan, R.O.C.
LANE2 MiniCard WLAN 7 Finger Title
LANE3 NewCard WLAN 8 NEW Reference
Size Document Number Rev
9 NC A3
Biwa -2
Date: Thursday, March 01, 2007 Sheet 2 of 42
A B C D E
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_CLKGEN_S0 2 1
2 1 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 2 1 R325 Do Not Stuff
1
1
1
1
R327 Do Not Stuff R318 Do Not Stuff C240 C234 C260 C263
Do Not Stuff
1
1
1
1
1
1
1
1
C492 C261 C264 C487 C235 C239 C265
DY C262 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
SC1U6D3V2ZY-GP
4 4
3D3V_S0
2
2
2
2
DY DY DY
R174 R180 R179 R173
10KR2J-3-GP Do Not Stuff Do Not Stuff Do Not Stuff
1
1
1
1
PCLKCLK2 U26
3D3V_CLKGEN_S0 2 55
VDDPCI SDATA SMBD_ICH 12,19
PCLKCLK3 3D3V_48MPWR_S0 9 56 SMBC_ICH 12,19
VDD48 SCLK
16 VDD
PCLKCLK4 53 VDDREF DREFCLK_1 RN21
DOTT_96/SRCT0 13 2 3 DREFCLK 7
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PCLKCLK5 31 14 DREFCLK#_1 1 CKS 4 SRN0J-6-GP DREFCLK# 7
VDDSRC DOTC_96/SRCC0
47 VDDCPU
17 DREFSSCLK_1 2 3 RN22 DREFSSCLK 7
SRCT1/SE1
2
2
2
2
3D3V_CLKPLL_S0 12 18 DREFSSCLK#_1 1 CKS 4 SRN0J-6-GP
DY RTM 20
VDDI/O96MHZ SRCC1/SE2 DREFSSCLK# 7
R162 R163 R164 R165 VDDPLL3I/O CLK_PCIE_SATA_1 RN23
-1 2/16 modify 26 VDDSRCI/O SRCT2/SATAT 21 2 3 CLK_PCIE_SATA 16
Do Not Stuff 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 37 22 CLK_PCIE_SATA_1# 1 CKS 4 SRN0J-6-GP CLK_PCIE_SATA# 16
VDDSRCI/O SRCC2/SATAC
41
1
1
1
1
VDDI/OCPU CLK_MCH_3GPLL_1 2 RN24
SRCT3/CR#_C 24 3 CLK_MCH_3GPLL 7
TP55
Do Not Stuff PCLKCLK0 1 25 CLK_MCH_3GPLL_1# 1 CKS 4 SRN0J-6-GP CLK_MCH_3GPLL# 7
PCI0/CR#_A SRCC3/CR#_D
3 TP99
Do Not Stuff PCLKCLK1 3 27 CLK_PCIE_MINI_12 2 3 RN25 CLK_PCIE_MINI1 28
3
PCI1/CR#_B SRCT4 CLK_PCIE_MINI_12#
SRCC4 28 1 CKS 4 SRN0J-6-GP CLK_PCIE_MINI1# 28
31 PCLK_KBC R171 2 1 22R2J-2-GP PCLKCLK2 4 PCI2/TME
PCI_STOP#/SRCT5 30 PM_STPPCI# 17
33 PCLK_SIO R178 2 1 22R2J-2-GP PCLKCLK3 5 29 PM_STPCPU# 17
PCI3 CPU_STOP#/SRCC5
SA SIV Bug 26 PCLK_PCM 1 R177 2 PCLKCLK4 6 PCI4/SRC5_EN SRCT6 33 CLK_PCIE_ICH_1 1 4 RN19 CLK_PCIE_ICH 17
CL=20pF