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SYSTEIIS L061C/PERIPHERAL




WD16C452, WD16C552

Dual Enhanced Asynchronous

Communications Element (ACE)

with Parallel Port




W. WESTERN DIGITAL
WD16C4521WD16C552


TABLE OF CONTENTS
Section Title Page
1.0 INTRODUCTION 2-1
1.1 Description 2-1
1.2 Features 2-1
1.3 General 2-1

2.0 SIGNAL DESCRIPTIONS 2-3

3.0 SERIAL CHANNEL REGISTERS 2-S
3.1 Serial Port Register Addressing 2-S

4.0 ACE OPERATIONAL DESCRIPTION 2-9
4.1 Master Reset ..... 2-9
4.2 ACE Accessible Registers 2-9
4.3 Line Control Register 2-12
4.4 ACE Programmable Baud Rate Generator 2-12
4.5 Line Status Register . . . . 2-15
4.6 Interrupt Identification Register 2-16
4.7 Interrupt Enable Register 2-18
4.S Scratch Pad Register 2-18
4.9 FIFO Control Register . 2-18

5.0 MODEM CONTROL REGISTER 2-19
6.0 MODEM STATUS REGISTER 2-20

7.0 PARALLEL PORT DESCRIPTION 2-21

S.O TYPICAL APPLICATIONS . . . 2-23



APPENDICES
Section Title Page
A.O DC OPERATING CHARACTERISTICS 2-25

B.O AC OPERATING CHARACTERISTICS AND TIMING DIAGRAMS 2-28

C.O PACKAGE DIAGRAM 2-40




11121/90 2-i
~D16C452~D16C552



LIST OF ILLUSTRATIONS
Figure Title Page
1-2 WD16C4521WD16C552 810ck Diagram ..... ..... 2-2
2-1 WD16C452IWD16C552 68-Pin QUAD Assembly Pin Designations 2-3
5-1 Interrupt Signal Logic . . . . . . . . . . . . . . . . . . 2-19
8-1 Typical Interface for a High-Capacity Data 8us ...... . 2-23
8-2 Typical 16-8it Microprocessor/RS-232 Terminal Interface Using the WD16C552 2-24
8-1 Receiver Timing . . . 2-29
8-2 Transmitter liming . . 2-30
8-3 MODEM Control Timing 2-31
8-4 Read Cycle Timing . . 2-32
8-5 Write Cycle Timing . . 2-32
8-6 RCVR FIFO Signaling Timing for First 8yte 2-34
8-7 RCVR FIFO Signaling Timing after First 8yte (R8R already set) 2-34
8-8 Receiver DMA Mode 0 liming (FCRO = 0 or FCRO = 1 and FCR3 = 0) 2-35
8-9 Receiver DMA Mode 1 Timing (FCRO = 1 and FCR3 = 1) . . . . . 2-35
8-10 Transmitter DMA Mode 0 Timing (FCRO = 0 or FCRO = 1 and FCR3 = 0) 2-36
8-11 Transmitter DMA Mode 1 (FCRO = 1 and FCR3 = 1) 2-36
8-12 Parallel Port Timing ....... . 2-37
8-13 WD16C452 Parallel Port Interrupt liming 2-38
8-14 WD16C552 Parallel Port Interrupt liming 2-38
C-1 68-Pin QUAD Plastic Package 2-40




2-ii 11/21/90
WD16C452IWD16C552


LIST OF TABLES
Table Title Page
2-1 Signal Descriptions 2-1
3-1 Register Addressing 2-8
4-1 Reset Control of Registers and Pinout Signals 2-9
4-2 Accessible WD16C4521WD16C552 Register 2-10
4-3 Baud Rates Using 1.8432 MHz Clock 2-13
4-4 Baud Rates Using 3.072 MHz Clock 2-13
4-5 Baud Rates Using 8.0 MHz Clock 2-14
4-6 Interrupt Control Functions 2-17
7-1 Parallel Port Register Addresses 2-21
7-2 Accessible Parallel Port Registers 2-21
7-3 Parallel Port Operation Modes 2-22
7-4 Parallel Port Reset Control of Registers and Signals 2-22
A-1 DC Operating Characteristics 2-26
A-2 Capacitance 2-27
B-1 WD16C4521WD16C552 Timing Diagrams 2-28
8-2 Receiver Timing 2-29
8-3 Transmitter Timing 2-30
8-4 MODEM Control Timing 2-31
8-5 Read/Write Cycle Timing 2-33
8-6 Parallel Port Timing 2-39




11121190 2-iii
i
I
INTRODUCTION WD16C4521WD16C552

1.0 INTRODUCTION
1.1 DESCRIPTION