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D D
Inventec Corporation
R&D Division
C C
Board name : Mother Board Schematic
Project : J11Eagle (Santa Rosa)
Version : 0.4
B
Initial Date : January 05, 2007 B
A A
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
J11Eagle(Merom+Crestline+ICH8M)
Size Document Number Rev
C 0.4
Title
Date: Monday, April 09, 2007 Sheet 1 of 55
5 4 3 2 1
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1. Schematic Page Description :
J11Eagle (Santa Rosa) Schematic Ver : 0.4
1. Title 26. OZ711MP1I(1/3) 51. USB BOARD
D D
2. Schematic Page DESCR 27. OZ711MP1I(2/3) 52. GLIDE SW BOARD W/FP
3. Block Diagram 28. OZ711MP1I(3/3) 53. STICK SW BOARD
4. ANNOTATIONS 29. LAN--88E8055 54. EMI/ESD
5. Schematic Modify 30. MINI_PCIE/USB/Bluetooth 55. GLIDE SW BOARD W/O FP
6. DDRII Layout Guideline 31. Audio Codec(1/2)
7. Merom Processor(1/2) 32. AUDIO JACK(2/2)
8. Merom Processor(2/2) 33. G-S/TPM1.2/SATA/MDC/BAY
9. CPU Thermal 34. BENN
10. Clock Generator 35. SUPER IO (1/2)
11. Crestline Host(1/6) 36. SUPER IO (2/2)
12. Crestline DMI/Graph2/6) 37. DVI Transmitter SiI1368
13. Crestline DDR2(3/6) 38. DOCK/KB/ST-LCD CN
C
14. Crestline Power(4/6) 39. RESET C
15. Crestline Power(5/6)* 40. CPU Core Power(MAX8770)
16. Crestline Ground(6/6) 41. LDO/SWITCH
17. DDR2 SDRAM SO-DIMM0 42. Battery
18. DDR2 SDRAM SO-DIMM1 43. Charger
44. 5VPMU/5VSTD/3VPMU/3VSTD
20. ICH8M PCI/PCIE/DMI(2/4) 45. 1.8V_DIMM
21. ICH8M GPIO(3/4) 46.GPU_CORE
22. ICH8M Power/GND(4/4) 47. BATTERY CN
23. BIOS/SMBUS_SW/80 PORT 48. 1.05V/ETC0
24. LCD&CRT 49. EC control
25. TV OUT & CRT SW 50. BAY TR /GP/Stick BOARD
B
2. PCI & IRQ & DMA Description : B
IDSEL CHIP
AD19 OZ711MP1
PCIINT CHIP
PCI_INT#0 OZ711MP1
PCI_INT#1 N/A
PCI_INT#2 N/A
PCI_INT#3 N/A
A
BUSMASTER A
REQ CHIP
REQ0 / GNT0 N/A
REQ1 / GNT1 OZ711MP1
REQ2 / GNT2 N/A Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
REQ3 / GNT3 N/A Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
J11Eagle(Merom+Crestline+ICH8M)
Size Document Number Rev
C 0.3
19. ICH8M CPU/IDE/SATA(1/4) Schematic Page DESCR
Date: Monday, April 09, 2007 Sheet 2 of 55
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3. Block Diagram :
PLL
CPU ICS9LPRS365BGLF
FAN1 PWM Thermal Thermal uFCPGA 478pin
P.10
D ADT7473 Merom D
P.9
P.9 P.7~8 166MHz+/- x2
100MHz+/- x9
FSB 1.05V 48MHz x1
667/800MHz 33MHz x6
LCD LVDS DDR2 1.8V 14MHz x2
SODIMM2
SODIMM1
MCH 35mmx35mm 533/667MHz 27MHz/96MHz+/-x1
P.24 S-OUT TVO 965GM/GML
P.25 FCBGA 1299pin
CRT CRT_SW DDR2 1.8V
RGB_CRT RGB
Crestline GM 533/667MHz
P.24
P.25
cPR2 RGB_DOCK P.11~16 P.17
P.38
P.18
DMI x4
cPR2 DVI SDVO
SI1368 RJ45
P.38 P.37 31mmx31mm P.29
ICH GbE SIM Slot
PCI-Express x1 2.5GHz
C mBGA 676pin 88E8055 Express P.30 C
ICH8M Port#1 P.29 Card MiniCard #1
PCI-Express x1 2.5GHz UMTS/Robson
HDD SATA 150 Port#2 P.27 MiniCard #2
PCI-Express x1 2.5GHz
P.33 Port#3
WLAN/Robson
P.30
PCI-Express x1 2.5GHz
PATA 100 Port#4 P.30
BAY
PCI 3.3V 33MHz
P.33
CardBus
OZ711MP1
USB3 USB2 USB1 USB0 P.26~28
CardBus MS/SD SmartCard
System4 System3 System2 System1 Slot Slot
P.26~28
USB Board USB Board USB Board P.30 P.26 P.28
EHCI#1
Support HDA 24MHz
B S0~S3 state AMP SPK
B
USB 2.0/1.1 Out
IntMic Out Audio P.32
P.31
USB5 USB4 MDC1.5 RJ11 Stereo Codec Out
P.32
Express P.33 P.33 IN cPR2
Docking ALC262 P.38
Card Analog In Out
P.38 P.27 P.32 IN Analog Out
P.31
P.32
USB 2.0/1.1
EHCI#2 LPC 3.3V 33MHz
Support
S0~S2 state
PMU&KBC ASIC Super I/O TPM 80Port
USB8 USB7 USB6 LUNA2 BENN LPC47N217 V1.2
MiniCard Finger
Bluetooth P.49 P.34 P.35-36 P.33 P.23
#0 Sensor
P.30 P.30 SW w/FP PS/2
cPR2 Serial
SPI P.38 P.36
P.19~22 KB
P.38 cPR2
Flash Flash ST-LCD P.38
P.38
ROM ROM Parallel
A A
P.36
FlatPoint StickPoint
P.23 P.23 IrDA
P.38 P.51
P.35
for_Finger for_BIOS
Sensor G-sensor
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
P.33 Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
App BTN BD J11Eagle(Merom+Crestline+ICH8M)
Size Document Number Rev
P.49 C 0.3
Block Diagram
Date: Monday, April 09, 2007 Sheet 3 of 55
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4. Nat name Description : Power Rail Destination Voltage S0 Current
PWR_CPUCORE MeromHFM: 1.3319V~1.4375V~1.4591V 36A
LFM: 0.9221V~0.9625V~0.9739V
Voltage Rails PWR_1.05VMAIN Merom: AGTL+ termination 0.997V~1.05V~1.102V 2.5A
965GM: Core 1.0V~1.05V~1.1V 4.6A
PWR_DCIN Primary DC system power supply 965GM: AGTL+ termination 0.9475V~1.05V~1.1025V 1.4A
+5VLA 5.0V always on power rail by LATCH or ACIN ICH8m:
D
PWR_3VSTD 3.3V always on power rail by LATCH or ACIN PWR_1.5VMAIN Merom PLL 1.425V~1.5V~1.575V 120mA
D
PWR_PMU 3.3V always on power rail by ECPWON 965GM: PCIE 1.425V~1.5V~1.575V 1.5A
PWR_5VSUS 5.0V power rail by SLP_S5#_3R 965GM: LVDS 1.425V~1.5V~1.575V 60mA
PWR_3VSUS 3.3V power rail by SLP_S5#_3R 965GM: TVDAC 1.425V~1.5V~1.575V 24mA
PWR_5VMAIN 5.0V switched power rail by SLP_S3#_3R 965GM: Various PLLS analog supply 1.425V~1.5V~1.575V 320mA
PWR_3VMAIN 3.3V switched power rail by SLP_S3#_3R 965GM: DDR DLLS,DDRII,FSB HSIO 1.425V~1.5V~1.575V 1.885A
ICH8m:
ICH8m:
PWR_CPUCORE Core Voltage for CPU ICH8m:
PWR_1.05VMAIN 1.05V power rail for AGTL+ termination/Core for GMCH by SLP_S3#_3R ICH8m:
PWR_1.5VMAIN 1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE Mini Card:
for ICH7m by SLP_S3#_3R Express Card:
PWR_1.8VSUS 965GM: DDRII System Memory 1.7V~1.8V~1.9V 3.1A
PWR_1.8VSUS 1.8V power rail for DDRII by SLP_S5#_3R SO-DIMM:
PWR_DIMM_VTT 0.9V DDRII Termination Voltage by SLP_S3#_3R 965GM: LVDS analog 1.7V~1.8V~1.9V 10mA
965GM: LVDS I/O 1.7V~1.8V~1.9V 60mA
Part Naming Conventions 965GM: PCIE analog 2mA
CLOCK GEN.
C = Capacitor
C CN = Connector PWR_DIMM_VTT DDRII Terminator: 0.855V~0.9V~0.945V 1.0A C
D = Diode
F = Fuse PWR_3VSUS 965GM: HV CMOS 3.135V~3.3V~3.465V 40mA
L = Inductor 965GM: TVDAC analog 3.135V~3.3V~3.465V 120mA
Q = Transistor ICH8m:
R = Resistor ICH8m:
RP = Resistor Pack ICH8m:
U = Arbitrary Logic Device ICH8m:
Y = Crystal and Osc ICH8m:
Mini Card:
Express Card:
CLK Generator: ICS9LPRS365AGLF 3.135V~3.3V~3.465V 400mA
Mini PCIe: WirelessLan
Net Name Suffix Azalia Codec: ALC262 3.0V~3.3V~3.6V
# = Active Low signal Azalia MDC:
HDD: SATA
965GM: CRT DAC 70mA
5. Board Stack up Description PWR_3VMAIN CardBus: OZ711MP1
CardBus: Slot voltage
3.0V~3.3V~3.6V
B PCB Layers Lan: Broadcom 88E8055
B
Card Reader: SD/MMC/MS
Layer 1 Component Side, Microstrip signal Layer Azalia MDC: For wake up
Layer 2 Ground Plane Mini PCI: For wake up
PWR_3VSTD ICH8m:
Layer 3 Stripline Layer ICH8m:
Layer 4 Power Plane ICH8m:
LCD: 3.0V~3.3V~3.6V 1.0A
Layer 5 Stripline Layer
Layer 6 Stripline Layer PWR_3VMAIN Azalia Codec: ALC262 3.0V~3.3V~3.6V
Azalia MDC:
Layer 7 Ground Plane HDD: SATA 4.75V~5.0V~5.25V Max: 1.0A ; R/W: 460mA ; STDBY: 70mA
Layer 8 Solder Side,Microstrip signal Layer ODD: PATA 4.75V~5.0V~5.25V Max: 1.8A ; R/W: 900mA ; STDBY: 45mA
Audio AMP: G1412
Single End Impedance Differential Impedance for Microstrip Differential Impedance for Stripline
Host Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
Woofer AMP: G1432
SRC Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
Inverter:
Host Bus 55 ohm +/- 15%
PWR_5VMAIN CardBus: Slot voltage
DDR2 CLK 42 ohm +/- 15% 70 ohm +/- 20% 70 ohm +/- 20%
USB: x 4 ports 5V 2.0A
DDR2 Strobe 55 ohm +/- 15% 85 ohm +/- 20%
PWR_3VSTD EC:
A
DDR2 Bus 55 ohm +/- 15%
ICH8m: RTC A
DMI Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
Flash ROM: BIOS
PCIE Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
SATA 95 ohm +/- 15% 100 ohm +/- 15% Inventec Corporation
SDVO 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15% 5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
LVDS 100 ohm +/- 15% 100 ohm +/- 15%
Title
USB 90 ohm +/- 15% 90 ohm +/- 15%
IEEE1394 110 ohm +/- 15% 110 ohm +/- 15% J11Eagle(Merom+Crestline+ICH8M)
Size Document Number Rev
C 0.3
Lan 50 ohm +/- 15% ANNOTATIONS
Date: Monday, April 09, 2007 Sheet 4 of 55
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6.Schematic modify Item and History :
V0.1 MODIFY LIST V0.3 MODIFY LIST
22. Change R772, R773 from 0 Ohm to 47 Ohm. (Page 32)
1. Change R75 from 10K to 100K. (Page 39)
23. Del R123, R124, R758, and mount R769. (Page 46)
2. Change R291 from 470K to NU. (Page 27)
D
24. Del U56, R320, R321, R287, C772, and mount R288, R308, R309, R310, R311, R312, R313 , and OZ711MP1 change to OZ711SP2(Page 26) D
25. LAN_RST# tie to GND.(Page 21)
26. Remove R189, R193 (Page 21)
V0.2 MODIFY LIST
1. ADD DVI function. (Page 37)
2. U27 pin K1 and M1 (AVCC) have to be connected from CORE_VCC to PCI_VCC. (Page 26)
3. DG_AMP_SD# change from U54 Pin 47 to U54 Pin 3. (Page 26)
4. R457,R468 change to 100 Ohm 1%, R462 change to 5.1K Ohm 1%, R127 change to 100K 1% add R758 0 Ohm---- Adjust OCP 10A (Page 45)
5. R98 change to 2.2K 0.5%, R93 change to 39K 0.5% ---- Adjust Changer current. (Page 48) V0.4 MODIFY LIST
6. Change X2 pin5 from GND to PWR_PMU (Page 34) 1. LAN_RST# pull down with 10K Ohm. (Page 21)
7. R102 change from 10K to 20K 1% ---- Adjust OCP 10A (Page 44) 2. Delete Pull-up(R2) for LAN_Disable.(Page 29)
8. Change R176 from 10K to 12K1% ---- Adjust OCP 7A (Page 47) 3. Delete RS1001, and A6,A7,D6,D7 tie to GND(SW with FP Page 52)
9. Change R616 from 4.7K to 475 Ohm ---- CLKREQ damping (Page 10) 4. ALG_HP_R_DOCK & ALG_HP_L_DOCK add 22K pull down, and change R59,R62 from 0 Ohm to 27K Ohm at V04. (Page 38)
10. R515 change from 1.3K to 1.27K ---- adjust CRT REFSET. (Page 12) 5. CN14 pin37 tie to GND. (Page 30)
11. Del R622 and change D35 (PP gate) from PWR_3VSTD to PWR_5VSUS, change D35 (P gate) from PWR_3VSTD to PWR_3VSUS --- improve leakage. (Page 22) 6. Change the G-sensor vender from ST-micro to KIONX. Change U14 and R101(1K)/R95 (NU) (Page 33).
12. R271 change from 3.48K to 3.9K, R238, R228 change from 2.1K to 2.67K.---- Ajust CPU Core load line (Page 39) 7. For Express Card leakage issue, please consider following. * U45 pin2 : From "PWR_3VMAIN" to "PWR_3VSTD". * U45 pin20 : From
13. Change R132 from 243 Ohm to 249 Ohm ---- Ajust PWR_3VMAIN_ATBG (Page 15). "SUSC#" to "PWR_3VSTD". * U44 pin5 : From "PWR_3VMAIN" to "PWR_3VSTD" (Page 28)
14. Change R433 ( 0 Ohm ) to NU. (Page 30) 8. Add U62(NU), R796 for SC_CD#, change R298 from NU to 10K, C398 from NU to 0.01uF, C391 from NU to 0.1uF. (Page26, 28)
15. Change R56 from 1K to NU.--- Set DOCK EXIST. (Page 34) 9. Change R691,R698 : 22K => 100K, C743,C749 : 1000pF => 220pF for the internal MIC volume small (Page 32)
C 16. Change R444 connect from DLY_SUSB# to DLY_SUSC#.--- Modify PWR_1.8VSUS power syquence. (Page 44) 10. Change C395 from NU to 470uF C
17. R293,R641,R642,R564,R569 change power plane from PWR_3VSUS to PWR_3VMAIN. ---- for S3 leakage. (Page 10) 11. Delete L72,L73,L74,L75 (Page 29)
18. CL_VREF1_ICH pull up change from PWR_3VSTD to PWR_3VMAIN. (Page 21) 12.Change C307,C311 from 10pF to 15pF. (Page 19)
19. R351 from 100K to NU ---- follow FJ schematics. (Page 47) 13. Add L72(100ohm bead)---NU, C890 (10uF)----NU for PWR_BL noise. (Page 24)
20. Add 470k ohm to LCDCL##_LUNA (Page 49) 14. Change R684 from 10K to 1K.(Page 44)
21. change Speaker lines dumping-resistersR391,R390,R389,R388 to Filter L66,L67,L68,L69. (Page 32) 15. Change R63,R64,R65 from 200 Ohm to 150 Ohm at V04 (Page 38)
22. C307, C311 change from 10PF to 15PF fro RTC. (Page 19) 16. Change C119 from 0.1uF to 1uF at V04 (Page30)
23. Add R759 470K, R758 0 Ohm. (Page49)
24. R673 change 10K to 220K. (Page 30)
25. C654,C655 change from 0.1uf/10V to 0.1uf/25V.
26. R214,R215 change from 0 Ohm to 2.2 Ohm.
27. Change R719,R721 from 10K to 12.4K (Page 31)
28. Add R767,R768 voltage divide to add "Maximum Power Clampping Function" to avoide damaging the speaker. (Page 31)
29. Change G-sensor from KXPS5-3176 to LIS302ALK (Page 33)
30. M_VREF add R760 0 Ohm to connect to U37 Pin6. (Page 45)
31. TP16 connect to change from PWR_DIMM_VTT to M_VREF. (Page 17)
32. Add C842~C867, C870~C876 for EMI.
33. Change Q53, Q54 from SI2301BDS-T1-E3 to RVE002P03. (Page 43)
34. U34 Pin5 change from PWR_3VSTD to PWR_5VMAIN. (Page 39)
35. C354,C359,C337,C674,C676,C679 change from NU to 5P 50V for EMI.
B
36. RS47,RS52,RS53,RS55 change from 2.2K to NU, RS29,RS30,RS48,RS54change from 1K to NU. (Page33) V0.2 Daughter Board Modify LIST B
37. Change R31: 47K => 1K, R37:4.7K => 1K, C63: 0.01uF => None 1.Change R1005 from 15K Ohm to 1.5K Ohm, and Net G_USBON add R1012 (NU) to CN1003 pin 14. (FingerPrinter Board)
38. Change R1,R2,C1,C2,U30 to NU (Page29) 2.C1011 change from U1001 Pin D8 to Pin D9.
39. R356 (0.01ohm )-> 0.015ohm, R33 (18k ohm)-> 12 k ohm, R28 (33k ohm ) -> 10k ohm, R24 (30k ohm)-> 39k ohm (Page43)
V0.3 MODIFY LIST V0.3 Daughter Board Modify LIST
1.Cut CN1-11pin & SW_GND1,then add zero-ohm resister between CN1-11pin & SW_GND1.(SW board)
1.Change Q113~Q120 from PDTC144EU to 2SC2412KR for SMBUS issue.
2.Change R1012 to NU (Finger Printer board)
2.Change LAN_DISABLE# pull-up from PWR_PMU to PWR_3VLAN, Change U30,R1,R2 from NU to install. Add L72,L73,L74,L75 common chock for EMI. (Page 29)
3.Mount: R1301, R1302, U1301, Remove: R1305, R1306 (FP board)
3.Change D35 Pin P from PWR_3VSUS to PWR_3VSTD (Page 22)
4. Add "L71" between these signals as below picture for reduce the noise on 1.5VS_TVDAC (Page 15)
5. Remove U41, U48, Mount R664. Add the Pull-up for "SPI_CE#0" with PWR_3VMAIN(RS31 Pin 4) (Page 23).
6. Change U18 from PI5V330SQE to PI5V330SQ1(Page 25) V0.4 Daughter Board Modify LIST
7. Change U50 from OZ2216S to OZ2206SN.(Page 27) 1. Delete RS1001, and A6,A7,D6,D7 tie to GND(Page 52)
8. Change C700 from 1000pF/NU to 0.01uF for TPS2231_CLKEN drop. (Page 28)
9. Add R773, R772 0 Ohm between L57, C419 & L56 & C420. Swap Q112 Pin S & Pin D(Page 32)
10. Add MS request the micrphone performance. (Page 32)
11. Change Bay con pin for move glide pad con. and stick con. to bay board. (Page 33)
12. Change RF_ON_SW from SW1 Pin3 to pin1. (page 34)
A 13.Please add R774 & D37, D36, change r733 from 10K to 1K to the DVI control signals. (Page 37) A
14. Change R63,R64,R65 from 75 to 200 fro VESA mesurement. (Page 38)
15. Add D38,D39 for discharge. (Page 39)
16. Change U26 PWRGD & CLKEN# pull up from PWR_3VMAIN. (Page 40) Inventec Corporation
17. Change R654 from 470K to 100K, and R646 from 47K to 10K. power on/off,S4 fail issue.(Page 41) 5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
18. Change circuit for fix PWR_BT1ROM/PWR_BT2ROM signals don't work issue. (Page 42) TEL:+886-2-2881-0721
19. Change GPU VID0~VID4 default from 00100 to 00010. (Page 46) Title
20. Add and reserve USB switch circuit (page 51)
Size
J11Eagle(Merom+Crestline+ICH8M)
Document Number Rev
21. Change U1002 from AAT4610AIGV to FPF2101, Add RS1001 for A6,A7,D6,D7 to GND. (Page 52) C 0.4
Schematic Modify
Date: Monday, April 09, 2007 Sheet 5 of 55
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8. Layout Guideline :
Crestline DDRII Layout Guidelines Control group : M_CKE[3..0],M_CS#[3..0],M_ODT[3..0] Data group : M_A_DQ[63..0],M_B_DQ[63..0],M_A_DM[7..0],M_B_DM[7..0]
DDRII Signal Groups 4/4 4/6
GMCH Escape
GMCH Escape
Group Signal Name Length Matching and Length Formulas
P1 L0 L1 L2 L3 Vtt P1 L0 L1 L2
D Data M_A_DQ[63..0]/M_B_DQ[63..0] Signal Group Minimum Length Maximum Length Breakout SL/MS Breakout D
M_A_DM[7..0]/M_B_DM[7..0] MS SL SL/MS S1 MS SL SL S1 MS
M_A_DQS[7..0]/M_A_DQS#[7..0] Control-to-Clock Clock - 1.0" Clock - 0.0" MS
M_B_DQS[7..0]/M_B_DQS#[7..0]
Command-to-Clock Clock - 1.0" Clock + 1.0" SO-DIMM SO-DIMM
Address M_A_A[13..0]/M_B_A[13..0]
M_A_BS[2..0]/M_B_BS[2..0] Strobe-to-Clock Clock - 0.5" Clock + 1.0"
M_A_RAS#/M_B_RAS# Topology Point-to-Point with parallel termination Topology Point-to-Point
M_A_CAS#/M_B_CAS# Data-to-Strobe Strobe - 220mils Strobe - 180mils
M_A_WE#/M_B_WE# Reference Plane Ground Reference Plane Ground
Control M_CS#[3..0] Characteristic Trace Impedance 55 +/- 15% L2 Seg.= 45Ohm +/- 15% Characteristic Trace Impedance 55 +/- 15%
M_CKE[3..0]
M_ODT[3..0] Nominal Trace Width Inner Layer : L3=5.5 mils, L5&L6= 7 mils Nominal Trace Width Inner Layer : L5&L6= 4.5 mils
Outer Layer : 5 mils Outer Layer : 5 mils
Clock M_CLK_DDR[3..0]
M_CLK_DDR#[3..0] Minimum CTRL Trace Spacing Inner Layer : 6 mils Minimum DQ Bus Trace Spacing Inner Layer : 6 mils
Outer Layer : 8 mils Outer Layer : 8 mils
FeedBack SA_RCVEN#/SB_RCVEN#
Minimum Spacing to Other DDR2 Inner Layer : 12 mils Minimum Serpentine Spacing Same as DQ-to-DQ routing
Outer Layer : 15 mils
Minimum Spacing to Other DDR2 Inner Layer : 12 mils
Minimum Isolation Spacing to non-DDR2 25 mils Outer Layer : 15 mils
Package Length P1 400~800 mils Minimum Isolation Spacing to non-DDR2 25 mils
Trace Length Limit - L0 Max = 250 mils (Escape) Package Length P1 750 mils +/- 350 mils
CLK group : M_CLK_DDR[3..0],M_CLK_DDR#[3..0] Trace Length Limit - L1 Max = 700 mils (Breakout) Trace Length Limit - L0 Max = 250 mils (Escape)
Stub Length S1-Stub from via to SO-DIMM Max = 250 mils (Breakin) Trace Length Limit - L1 Max = 700 mils (Breakout)
4/4/12 7/4/16 8/5/15
SO-DIMM MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils Stub Length S1-Stub from via to SO-DIMM Max = 250 mils (Breakin)
GMCH Escape Max = 4500 mils
From GMCH ball to SO-DIMM pad MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils
P1 L0 L1 L2 S1 Total Length - P1 + L0 + L1 + L2 + S1 - Max = 5000 mils From GMCH ball to SO-DIMM pad Max = 4500 mils
From GMCH die to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 - Max = 4800 mils
C
P1 L0 L1 L2 S1