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8 7 6 5 4 3 2 1
Version 1.0
Cover Sheet
Block Diagram
1
2
MS-6399 07/23/2001 Update
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock CY28323 & ATA100 IDE CONNECTORS 4
mPGA478-B INTEL CPU Sockets 5-6
INTEL Brookdale MCH -- North Bridge 7-8
INTEL ICH2 -- South Bridge 9 - 10
LPC I/O W83627HF 11 CPU:
Willamette/Northwood mPGA-478B Processor
PCI AUDIO-CMI8738 12
AUDIO CONNECTOR 13
C
System Brookdale Chipset: C
Audio Amp TL072 & GAME 14
INTEL MCH (North Bridge) +
FWH -- BIOS & VCC_VID 15 INTEL ICH2 (South Bridge)
SDR DIMM-168PIN DIMM1,2 16 On Board Chipset:
AGP 4X SLOT (1.5V) 17 BIOS -- FWH
PCI SLOT 1 & 2 & 3 18 LPC Super I/O -- W83627HF
Front Panel & Connectors 19 Clock Generation -- CY28324
USB & FAN Connectors 20 PCI SOUND -- C-MEDIA CMI8738
B B
Votlage Regulator 21
HIP6301V CPU Power ( PWM )-VRM9.0 22 Expansion Slots:
AGP2.0 SLOT * 1
IO Connectors 23
PCI2.2 SLOT * 3
Realtek RTL8100(L) LAN 24
JUMPER SETTING 25
MANUAL 26
LAYOUT GUIDE
A A
Title Rev
M i c ro-Star MS-6399 1.0
Document Number
Cover Sheet
Last Revision Date:
Monday, July 23, 2001 Sheet 1 of 31
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.0 Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
AGP 4 X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) (133MHz)
DIMM 1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Heceta Hardware SM Bus C
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Audio /
(48MHz) C-MEDIA SPDIF
CMI8738 IN/OUT
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3 CNR Riser
(Shared slot)
AC '97 Audio
FWH: Firmware HUB AMP
Codec
PCI LAN / SIO
Realtek Line Out
Telephone In
RTL8100L MIC In
B
Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
CD-ROM
Keyboard Serial (2) Drive CONN
A A
Title Rev
M i c ro-Star MS-6399 1.0
Document Number
Block Diagram
Last Revision Date:
Monday, July 23, 2001 Sheet 2 of 31
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2
GPIO Pin Type Function
GPIO 0 I Non Connect
GPIO 1 I Non Connect
GPIO 2~4 I Not Implemented
DEVICE ICH INT Pin IDSEL
GPIO 5 I Non Connect
GPIO 6 I AC97 Enabled/Disabled
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 8 I LAN Wake Up INTD#
GPI 1 I ATA IDE 2 Detect
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
PCI Slot 3 INTC# AD18
GPIO 13 I LPC PME
INTD#
GPIO 14~15 I Not Implemented INTA#
INTB#
GPIO 16 O Non Connect
GPIO 17 O Non Connect PCI Audio INTD#/INTE# AD23
INTA#
B
GPIO 18 O Not Implemented B
INTB#
GPIO 19 O Not Implemented INTC#
GPIO 20 O Non
PCI Lan INTC#/INTF# AD22
GPIO 21 O Not Implemented INTD#
INTA#
GPIO 22 O Non
INTB#
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
GPIO 25 O Non
GPIO 26 O Non
GPIO 27 I/O Non
A A
GPIO 28 I/O Non
GPIO 29~31 I/O Not Implemented
Title Rev
M i c ro-Star MS-6399 1.0
Document Number
GPIO Spec.
Last Revision Date:
Monday, July 23, 2001 Sheet 3 of 31
5 4 3 2 1
8 7 6 5 4 3 2 1
for good filtering from 10K~1M
*Trace less 0.5"
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
CP8 X_COPPER
CPUCLK R233 49.9RST
U18 CPUCLK# R234 49.9RST
FB18 39 41 R246 33 CPUCLK MCHCLK R229 49.9RST
VCC3 X_0/0805 CPU_VDD CPU0 CPUCLK 5
40 R247 33 CPUCLK# MCHCLK# R230 49.9RST
+
CB145 CPU0# CPUCLK# 5
Rubycon CT34 CB144 CB154 ITP_CLK R232 X_49.9RST
104P 105P 104P 36 38 R239 47 MCHCLK ITP_CLK# R236 X_49.9RST
CPU_GND CPU1 37 R240 47 MCHCLK 7
MCHCLK# MCHCLK# 7
CN16
D X_ELS10U/16V-B CPU1# D
46 8P4C-10P
MREF_VDD 45 C_STP R243 X_33 ITP_CLK MCH_66 1 2
CB151 3VMREF/CPU_STP# 44 P_STP R244 X_33 ITP_CLK#
ITP_CLK 5 Trace less 0.2" ICH_66 3 4
104P 43 3VMREF#/PCI_STP# ITP_CLK# 5
49.9ohm for 50ohm M/B impedance AGPCLK 5 6
MREF_GND 7 8
for good filtering from 10K~1M 32 31 1 2 MCH_66 MCH_66 7
3V66_VDD 3V66_0 30 RN17 3 4 ICH_66 CN18
3V66_1 ICH_66 10
CP9 X_COPPER CB153 28 8P4R-33 5 6 AGPCLK 8P4C-10P
R228 104P 29
3V66_GND
3V66_2
3V66_3
27 7 8 C157 10P AGPCLK 17 CLOCK STRAPPING RESISTORS SIO_PCLK 8 7
X_0 RN25 FWH_PCLK 6 5
6 FS2 7 8 ICH_PCLK 4 3
FB20 X_0/0805 VCC3V 9 FS2/PCI_F0 7 FS3 5 6 ICH_PCLK FS4 R324 10K VCC3V 2 1
VCC3 PCI_VDD FS3/PCI_F1 8 ICH_PCLK 9
MODE 3 4 FWH_PCLK FS3 R334 10K VCC3V
+
MODE/PCI_F2 FWH_PCLK 15
CB166 Rubycon CT36 CB178 CB183 1 2 SIO_PCLK CN17
104P 105P 104P 5 10 SIO_PCLK 11
FS4 8P4R-33 FS1 R282 X_10K VCC3V 8P4C-10P
PCI_GND FS4/PCI0 11 R308 33 PCICLK4 R283 10K PCICLK0 7 8
ELS10U/16V-B PCI1 R449 33 PCICLK4 12
18 12 PCICLK5 PCICLK5 18 PCICLK1 5 6
PCI_VDD PCI2 14 7 8 PCICLK0 PCICLK2 3 4
CB177 PCI3 15 RN24 5 6 PCICLK1 PCICLK0 18
PCICLK1 18 FS0 R321 10K VCC3V PCICLK3 1 2
104P 13 PCI4 8P4R-33 3 PCICLK2 R322 X_10K
16 4 PCICLK2 18
PCI_GND PCI5 17 1 2 PCICLK3 PCICLK4
*Put GND copper under Clock Gen. PCI6 PCICLK3 24
FS2 R326 X_10K C176 10P
connect to every GND pin 24 R325 10K VCC3V
48_VDD 22 FS0 R307 33 ICH_48 PCICLK5 C177 10P
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 10
CB164 23 FS1 R281 33 SIO_48 MODE R336 X_10K
with GND copper around it 104P 21 FS1/24_48MHz SIO_48 11 AUDIO_14 C179 10P
48_GND
* put close to every power pin 2
C C
REF_VDD 48 MUL0 R251 33 ICH_14 MUL0 R241 X_10K VCC3V ICH_48 C175 X_10P
* Trace Width 7mils. CB165 MUL0/REF0
1 MUL1 R314 33 AUDIO_14 ICH_14 10 R231 10K SIO_48 C169 10P
MUL1/REF1 AUDIO_14 12
104P 47
* Same Group spacing 15mils REF_GND MUL1 R316 10K VCC3V
34 3 C171 18P R315 X_10K
* Different Group spacing 30mils CORE_VDD X1 32pF
CB152 X1 14.318MHZ/32PF
* Different mode spacing 7mils on itself 104P 33 4 C166 18P CRST# R305 10K VCC3V ICH_14 C164 10P
CORE_GND X2
10,11,16 SMBCLK SMBCLK 26 35 R227 475RST
R323 VTT_GD# SMBDATA 25 SCLK IREF SMBCLK R255 1K
VCC3
10K
10,11,16 SMBDATA SDATA 20 CRST# R306 X_0 FP_RST# SMBDATA R254 1K VCC3 used only for EMI issue
RST# FP_RST# 5,19
R318 X_1K
VTT_GD# 19 42 R245 4.7K VCC3V
VCC3V Trace less 0.2"
Q36 VTT_GD# PWR_DN#
VCCP 2N3904S CY28323 REV.A C_STP R242 X_1K VCC3V
R304 220 ICS950208 P_STP R235 X_1K
CY28323
+12V Q56
X_2N3904S
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
R480 X
R481 ATA100 IDE CONNECTORS
X R190 X_4.7K IDE1 R186 X_4.7K IDE2
YJ220-CB-1 YJ220-CW-1
HD_RST# R188 33 1 2 HD_RST# R187 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B 10 PDD[0..7] PDD6 PDD9 PDD[8..15] 10 10 SDD[0..7] SDD6 SDD[8..15] 10 B
5 6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
10 PD_DREQ 21 22 10 SD_DREQ 21 22
10 PD_IOW# 23 24 10 SD_IOW# 23 24
10 PD_IOR# 25 26 10 SD_IOR# 25 26
27 28 R129 470 27 28 R128 470
10 PD_IORDY 29 30 10 SD_IORDY 29 30
10 PD_DACK# 10 SD_DACK#
9 IRQ14 31 32 9 IRQ15 31 32
10 PD_A1 33 34 PD_DET 15 10 SD_A1 33 34 SD_DET 15
10 PD_A0 35 36 PD_A2 10 10 SD_A0 35 36 SD_A2 10
10 PD_CS#1 37 38 PD_CS#3 10 10 SD_CS#1 37 38 SD_CS#3 10
R189 33 39 40 R101 33 39 40
19 PD_LED 19 SD_LED
C79 R119 C76 C81 R120 C77
VCC5 R191 8.2K 47P 10K X_473P VCC5 R103 8.2K 47P 10K X_473P
VCC3 VCC3
R407 1K VCC5
A RESET BLOCK PCIRST# 9 8 HD_RST# A
U21D
7407S
R388 330 VCC3 (VCC5_SB) R197 330 VCC3 Title Rev
9 PCIRST#
PCIRST# 1 2
PCIRST#1 7,11,12,15,24
PCIRST# 3 4
PCIRST#2 17,18
M i c ro-Star MS-6399 1.0
U21A U21B Document Number
7407S C199 7407S
Clock CY28323/4 & ATA100 IDE
(VCC5_SB) (VCC5_SB)
X_10P Last Revision Date:
Tuesday, July 24, 2001 Sheet 4 of 31
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCPS+ 22 VCCP
7 HA#[3..31] VCCPS- 22
ITP_CLK# 4 R81
ITP_CLK 4
ITP_DB #
2/3*Vccp 49.9RST
R
VID[0..4] 11,22
GTLREF1
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VID2
VID0
VID4
VID3
VID1
C49 C48 C58 R79
220P 220P 105P 100RST
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
U7A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#