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A B C D E




PCB LAYER
DC/DC IMVP4
Switching Power
ISL6218 32
MOLOKAI Block Diagram L1:COMPONENT
L2:GND
INPUTS OUTPUT SPR.01.2004 CPU Project Code:91.43E01.001 L3:SIGNAL1
4 DCBATOUT VCC_CORE Banias/Dothan 4

L4:SIGNAL2
03249-SC
SYSTEM DC/DC CLOCK 5,6 L5:VCC
Generator
MAX1715 34 ICS950810 3 HOST BUS L6:GND
INPUTS OUTPUTS 100MHz CRT 13 L7:SIGNAL3
1D35V_S0 L8:COMPONENT
DCBATOUT DDR 266/333 DVO CH7011 TV_OUT
2D5V_S3 DDR Montara-GM+ (CHRONTEL)
DRAM 7,8,9
15
10,11,12
Socket
DC/DC&CHARGER *2 LVDS
LCD POWER SW
MAX1645
Hub I/F 14

TPS2220A
35 Ultra 20
3 DMA-100 PCI BUS 3

INPUTS OUTPUTS HDD 26
SD/MS CARD CARDBUS
AD+ BT+ IDE BUS ICH4-M READER + 1394 SLOT B 22




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OPTICAL 16,17,18 PCI7420 21
USB2.0
CardReader
DC/DC LPC BUS
MAX1999 33 1394




USB2.0
INPUTS OUTPUTS
3D3V_S5 BIOS KBC MINIPCI
DCBATOUT 5V_S5 ROM M38859 LAN 802.11B
49LF004-334C BCM4401
27 28 23 802.11G 19


2
AC-LINK 2

USB 2.0 Line-out
G913C/APL1085
APL5331kAC/G1211X
38
2 Ports RJ-45
29
INPUTS OUTPUTS MODEM
TOUCH INT AC 97 MIC
3D3V_S0 1D8V_VCCA_S0 DAUGHTER
3D3V_S5 1D5V_S5 PAD KB CARD Codec
3D3V_S0 1D5V_S0 29 STAC9750
2D5V_S3 1D25V_S0
1D35V_S0 VCC_IO_S0
24
RJ-11 Amplifier
(TBD)
TPA0312 25




1
Digitally signed by 1

fdsf Wistron Corporation
DN: cn=fdsf, o=fsdfsd, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ou=ffsdf, Title

email=fdfsd@fsdff, Size
BLOCK DIAGRAM
Document Number Rev
c=US Wistron Confidential
A3
MOLOKAI SC

A B
Date: 2010.03.29
C D
Date: Monday, April 05, 2004 Sheet

E
1 of 39


18:09:00 +07'00'
A B C D E




S5 S3 S0
5V_S0 5V_S0 13,14,17,18,19,20,24,26,28,30,32,34,36,38,39
5V_S5 5V_S5 18,33,34,36
3D3V_S0 3D3V_S0 3,7,8,9,10,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,30,31,32,36,38,39
3D3V_S5 3D3V_S5 4,16,17,18,28,30,31,33,36,38,39 3D3V_S3 3D3V_S3 14,25,28,30,34,36,39

1D5V_S5 1D5V_S5 18,38 2D5V_S3 2D5V_S3 7,9,10,11,34,38,39
1D5V_S0 1D5V_S0 7,8,9,15,16,18,27,38,39
VCC_RTC_S5 VCC_RTC_S5 17 1D25V_DDRVREF_S3 1D25V_DDRVREF_S3 7,10,34
4 1D25V_S0 1D25V_S0 11,12,38 4

1D35V_S0
1D35V_S0 7,9,34,38,39

VCC_CORE_S0 VCC_CORE_S0 6,32,39

VCC_IO_S0 VCC_IO_S0 4,5,6,7,9,17,18,32,38,39

AC-IN / BAT.-IN LAN-AC 1D8V_VCCA_S0 1D8V_VCCA_S0 5,38


AD+ AD+ 35,37,39

DCBATOUT DCBATOUT 14,32,33,34,35,36,38,39 3D3V_LAN_S5AC 3D3V_LAN_S5AC 23,29,36,37 5VA_AUD_S3 5VA_AUD_S3 24
AUDIO


3D3V_LCD_S0 3D3V_LCD_S0 14 LCD


CRT_VCC_S0 CRT_VCC_S0 13 CRT


TV3D3V1_S0 TV3D3V1_S0 15

TV3D3VA_S0 TV3D3VA_S0 15 TV-OUT
3 3
TV3D3V2_S0 TV3D3V2_S0 15

OTHERS TV1D5V_S0 TV1D5V_S0 15




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5V_AUX 5V_AUX 30,31,33,35,37,38,39

3D3V_AUX 3D3V_AUX 14,17,33




3D3V_RTC 3D3V_RTC 17,28

ICH_VBIAS ICH_VBIAS 17

MAX1999_REF MAX1999_REF 33,38



MAX1999_VCC MAX1999_VCC 33




2 2




PCI TABLE

DEVICE IDSEL IRQ REQ# / GNT#


PIRQB#
SD/MS CARD READER+1394 AD20 PIRQC# REQ#1 / GNT#1
PIRQF#
PCI7420

1 MINI PCI 802.11B/G AD17 PIRQE# REQ#0 / GNT#0 1
PIRQG#
Wistron Corporation
LAN BCM4401 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AD21 PIRQD# REQ#4 / GNT#4 Taipei Hsien 221, Taiwan, R.O.C.

Title
Table of Content
Size Document Number Rev
A3 SC
MOLOKAI
Date: Saturday, April 17, 2004 Sheet 2 of 39

A B C D E
R208
PLACE NEAR EACH PIN
3D3V_S0 1 2 CLKGEN_+3VRUN
3D3V_S0 Filtering CKT for 0R5J-1




1




1




1




1




1




1




1




1
Host Freq. Setting 48MHz power plane
R192 BC139 BC237 BC238 BC228 BC239 BC141 BC231 BC227
1 2 CLKGEN_48MPWR SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1




2




2




2




2




2




2




2




2
FS1/0 = 00 166MHz




1




1




1
FS1/0 = 01 100MHz 0R5J-1 DUMMY-SC10U10V5ZY
BC145 BC128 BC229 BC230
FS1/0 = 10 200MHz SCD1U16V SCD01U16V2KX SCD1U10V2MX-1




2




2




2
FS1/0 = 11 133MHz R218

SC10U10V5ZY CLKGEN_APWR 1 2 3D3V_S0
FS2 = 0 unbuffer mode (disable 66MHz-IN) 0R5J-1




1




1
FS2 = 1 buffer mode
BC142 BC143 BC144
SCD1U10V2MX-1 SCD01U16V2KX DUMMY-SC10U10V5ZY




2




2
Mult0 = 0 Rr=221,Iref=5mA =>Vswing=1.0V@50ohm No stuff: U40
Mult0 = 1 Rr=475,Iref=2.32mA =>Vswing=0.7V@50ohm caps are internal
1 26
to CK-TITAN. VDDREF VDDA RN26 SRN33-2-U2
8 CLK_CPU 5
VDDPCI R160
CPU & MEMORY Freq. Selection BC140 14 27 1 4 1 2 49D9R3F
VDDPCI GND R161
2 1 19 2 3 1 2 49D9R3F
3D3V_S0 VDD3V66
32 45 CLK_CPU# 5
DUMMY-SC10P50V2JN-1 VDD3V66 CPUCLKT2 RN25 SRN33-2-U2
37 44 CLK_MCH 7
3D3V_S0 VDD48 CPUCLKC2




2
46 1 4 R158
1 2 49D9R3F
X2 VDDCPU R159
50 49 2 3 1 2 49D9R3F
VDDCPU CPUCLKT1
1




48 CLK_MCH# 7
X-14D31818M-7 CPUCLKC1
1




1




2 RN24 DUMMY-SRN33-2-U2 R155 1 2 DUMMY-R2
X1 CLK_ITP_CPU 4,5




1
R483 R185 R181 BC127 52 1 4 CLK_ITP_R R154
1 2 DUMMY-49D9R3F
10KR2 1KR2 DUMMY-R2 CPUCLKT0 R157
2 1 3 51 2 3 CLK_ITP#_R 1 2 DUMMY-49D9R3F
R187 1KR2 X2 CPUCLKC0 R156 1 2 DUMMY-R2 CLK_ITP_CPU# 4,5
DUMMY-SC10P50V2JN-1 1 2 SEL2 40 24 TP90
FS2 3V66_5
2




2




2




23 TP89
CK-408 3V66_4 TPAD28
CK-408_MULT0 55 22 R217
TPAD28 1 2 33R2




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FS1 3V66_3 CLK66_GMCH 8
21 R216 1 2 33R2
3V66_2 CLK66_ICH 16
1




54
FS0
1




1




R484 25 7 R209 1 2 33R2
17 PM_SLP_S1# PD# PCICLK_F2 CLKPCIF_ICH 17
DUMMY-R2 R182 34
1KR2 17 PM_STPPCI# PCI_STOP#
R184 53 6 TP86
17,32 PM_STPCPU# CPU_STOP# PCICLK_F1
DUMMY-R2 28 TPAD28
32 CLK_PWD# VTT_PWRGD#
2




CK-408_MULT0 43 5 TP84
MULTSEL0 PCICLK_F0
2




TPAD28
2




SMBD_ICH 29 18 TP88
10,17 SMBD_ICH SDATA PCICLK6
10,17 SMBC_ICH SMBC_ICH 30 TPAD28
SCLK R215 1
17 2 33R2 PCLK_CBUS 21
R191 1 PCICLK5
8 CLK66_DREF_GMCH 2 33R2 33
3V66_0 R214 1
35 16 2 33R2 PCLK_KBC 28
R603 1 3V66_1/VCH_CLK PCICLK4
2 DUMMY-33R2
1 R186 2 42 13 R213 1 2 33R2
IREF PCICLK3 PCLK_FWH 27
R190 1 2 33R2 475R3F
21 CLK48_DOT
41 12 R212 1 2 33R2
GND PCICLK2 PCLK_MINI 19
02/09/2004 11 R211 1 2 33R2
PCICLK1 PCLK_LAN 23
4
GND TP182 TPAD28
9 10
GND PCICLK0
15
GND R188 1
20 39 2 33R2 CLK48_ICH 16
GND 48MHZ_USB
31
GND R189 1
36 38 2 33R2 CLK48_DREF_GMCH 8
GND 48MHZ_DOT
47
GND R183 1
56 2 33R2 CLK14_ICH 17
REF
R655 1 2 DY-33R2 CLK14_AUDIO 24
ICS950810CG

SC:Because codec 01/15/2004
change to use
crystal so dummy
CLK source




Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Clock GEN.
Size Document Number Rev
A3 SC
MOLOKAI
Date: Thursday, April 15, 2004 Sheet 3 of 39
A B C D E




4 4




ITP Debug Pad

VCC_IO_S0 VCC_IO_S0



CPU ITP Conn.




1

1




1




1
R454 R440 R456 R442
150R2
54D9R3F 54D9R3F 39D2R3F
TPAD28 TP60




2

2




2




2
TDI_FLEX TPAD28 TP63
5 H_TDI
5 H_TMS TMS_FLEX TPAD28 TP71
TRST_FLEX TPAD28 TP62 TCK(PIN 5)
5 H_TRST#
TCK_FLEX TPAD28 TP61
3 5 H_TCK R441 3
1 2 TDO_FLEX TPAD28 TP64
5 H_TDO DUMMY-22D6R3F TPAD28 TP9
3,5 CLK_ITP_CPU# CLK_ITP_CPU# TCK(PIN A13)
CLK_ITP_CPU TPAD28 TP8
3,5 CLK_ITP_CPU
R453 H_TCK TPAD28 TP67




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GTL_CPURST# 1 2 RESET_FLEX# TPAD28 TP66 FBO(PIN 11)
5,7 GTL_CPURST# DUMMY-22D6R3F TPAD28 TP17
5 H_BPM5_PREQ#
1
TPAD28 TP74
5 H_BPM4_PRDY#
R439 3D3V_S5 TPAD28 TP16
27D4R3F 5 H_BPM3_ITP#
TPAD28 TP70
5 H_BPM2_ITP#
2




1
Should place near conn.
R455 TPAD28 TP73
150R2 5 H_BPM1_ITP#
TPAD28 TP13
2 5 H_BPM0_ITP#
TPAD28 TP68
5 ITP_DBRESET# VCC_IO_S0 TPAD28 TP69
TPAD28 TP65




1
TPAD28 TP72
C365
DUMMY-SCD1U10V2MX-1




2
2 2




1 1


Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ITP
Size Document Number Rev
A3 SC
MOLOKAI
Date: Thursday, April 15, 2004 Sheet 4 of 39

A B C D E
A B C D E


CPU VCCA POWER: 7 GTL_D#[15..0] U68C
GTL_D#[47..32] 7
At Dothan CPU application, POWER is 1.5V or 1.8V.
GTL_D#15 C25 Y25 GTL_D#47
D15# D47#
GTL_D#14 E23 AA26 GTL_D#46
1D8V_VCCA_S0 D14# D46#
For CPU VCCA[0:3] PLL GTL_D#13 B23