Text preview for : 2801 Mesatronic.pdf part of Keithley 2801 Mesatronic Keithley Appnotes 2801 Mesatronic.pdf
Back to : 2801 Mesatronic.pdf | Home
WHITE
PA P E R
Advanced Membrane Substrate and Interconnects
Will Allow Simultaneous RF and DC Measurements
During Wafer Probing
Background
Traditionally, probe cards for parametric testers have been designed for either
RF signals or low level DC measurements, but not both. This was fine as long
as a semiconductor wafer contained only RF test circuits, or those designed
for DC operation. However, as digital switching speeds have increased to RF
frequencies, and mixed RF and DC test devices are designed into wafers,
separate RF and DC probing has become very costly. It requires a changeover
from one type of probe card to the other, recalibration of the parametric
tester and its interconnects, and then re-probing the wafer for a second set of
measurements.
In addition, on-wafer testing of semiconductor devices often utilizes the
interfacing between test instruments and the test points and structures located
within wafer scribe lanes. As semiconductor dies and scribe lanes decrease
in size, it becomes more difficult to connect test instruments to the device
under test (DUT). This problem is compounded when both RF and ultra-low
current DC measurements are desired. In RF measurements, an important
consideration is minimizing RF signal losses through a variety of techniques,
such as maintaining the desired characteristic impedance to minimize RF
energy reflections along the signal path. In ultra-low current measurements (for
Keithley Instruments, Inc.
28775 Aurora Road
Cleveland, Ohio 44139
(440) 248-0400
Fax: (440) 248-6168
www.keithley.com
A G r e A t e r M e A s u r e o f C o n f i d e n C e
example, sub-nanoamp magnitudes), it is important to minimize the effects of extraneous
voltage potentials in the vicinity of the test point.
To help alleviate this situation, some probe cards have recently been designed for a
few RF connections, with the remaining probes calibrated for DC. This helps to some extent
but limits the effectiveness of parametric test systems, most of which could be programmed to
conduct either RF or DC measurements on any pin. Still, parametric testers themselves need to
be designed so that interconnections on any signal path can handle either type of signal. Up to
now, this type of system has not been available.
However, Keithley Instruments and Mesatronic Group (Voiron, France) have formed
a technical alliance that is blazing new trails in the quest for small geometry, mixed RF and
DC testing. Engineers from the two companies are working together to create probe cards
for parametric test systems that take RF and low level DC measurements on any combination
of wafer prober pins. Project objectives include easier layout and manufacture of the probe
cards, shorter production times, and ultimately lower cost to parametric test users. In addition,
users should be able to reduce their probe card inventory by using one card design for many
different applications.
Semiconductor Wafer Trends
Because of today's fast switching digital devices and their combination with RF analog
devices on the same wafer, wafer level RF testing is needed to predict product performance
and reliability. Still, DC parametric testing remains just as important as ever in detecting
phenomena that affect device lifetimes and failure modes. As the industry progresses toward
the 65nm node and beyond, high-performance/low-cost digital, RF, and analog/mixed-signal
devices present a significant challenge to test equipment and probe card manufacturers. The
big challenge in parametric tester design is to combine the measurement of GHz frequencies
and femtoamp DC signals in a way that helps improve device reliability while lowering
test costs.
At the same time, a challenge for probe card manufacturers is the continuous shrinking
of wafer scale dimensions to allow more devices per unit area. This includes shrinking scribe
lanes on wafers, which are currently trending toward a 30-micron width. That means probe
pads must be just as small or smaller. Card designs must incorporate probe needles that can
hit these smaller targets without excess scrubbing motion that causes a probe tip to go off the
pad. Currently, conventional cantilever probe technology is restricted to pad sizes larger than
50 microns.
A G r e A t e r M e A s u r e o f C o n f i d e n C e
Implications For Parametric Testers
For the past few years, manufacturers of parametric testers have been grappling with the
technical problems of mixed RF and low level DC measurements. A prerequisite for accurate
measurements is the creation of a low-loss broadband signal path and good calibration
techniques. The key element in effective calibration is fast, automatic de-embedding of probe
pad/interconnect impedance that impairs data integrity. When used with a suitable probe
card design and test structures on the wafer, a well designed and calibrated parametric tester
should be able to execute independent DC and RF tests in parallel on separate probes, greatly
reducing the time and cost of testing.
However, an "any pin" RF/DC measurement objective faces several technical
hurdles. Most of these are associated with interconnections along the signal path and system
calibration, which involves wafer test pads, probe pins, the probe card, interconnecting cables,
and the parametric tester itself. To successfully probe high frequency and sensitive DC
devices, one must master the mechanical and electrical properties of the signal path.
Physically, a probe card is a circuit board. At high frequencies, probe cards become
transmission lines, so a major consideration is how they affect signal propagation (for example,
RF energy reflections), interaction between signals (crosstalk), and interactions with the
outside world (in the form of electromagnetic interference). These and other considerations,
such as wave phenomena, are related to the characteristic impedance of the signal path and
any mismatch that occurs at the signal source or measurement end.
Keithley/Mesatronic Spatial Transformer Development
Keithley Instruments has partnered with Mesatronic to develop advanced probe cards for
parametric test and production applications. When the project is completed, the new cards can
be used to measure RF signals and very low level DC currents on any combination of probe
pins that contact a semiconductor wafer. Moreover, the probes for these cards will be suitable
for 30-micron test pads.
These cards should be of particular interest to manufacturers of RFICs (RF integrated
circuits), RFIDs (radio frequency identification devices), and devices for mobile and wireless
handsets and infrastructure. Currently, there are very few probe card technologies available
that allow single insertion RF and low current DC measurements, and RF measurements are
limited to only a few dedicated probe pins that cannot be used for accurate low current DC
measurements.
The Keithley/Mesatronic collaboration is concentrating on development of the spatial
transformer that is used as an interconnection between test instruments and probe needles or
A G r e A t e r M e A s u r e o f C o n f i d e n C e
membranes that make actual contact with the DUT on the wafer. Thus, the spatial transformer
serves as an intermediate structure that concentrates the test instrument connections into a
form more suited to the high density inputs of the needles or membrane.
When both RF and precision DC measurements need to be made, the practice in the
past has been to use a specially designed spatial transformer for each desired combination
of RF and DC test terminals. Each RF connection uses RF terminals having a desired
characteristic impedance and each precision DC connection uses a "guarded" terminal to
minimize leakage currents. This greatly complicates and increases the cost of obtaining a
suitable spatial transformer.
A key feature of the Keithley/Mesatronic spatial transformer design is the creation of
"broadband guarding." As with other types of guarding, the appropriate points along the signal
path are effectively surrounded with elements at the same voltage as the points of interest.
This prevents them from "seeing" any other potentials that would cause DC leakage currents
and measurement inaccuracies. However, the Keithley/Mesatronic development goes a step
further. The guard traces on the spatial transformer, in combination with the center conductor
traces, also provide the desired characteristic impedance for an RF signal traveling along the
same signal path.
Keithley's expertise in sensitive DC and RF measurement guard circuitry and other
interconnect technology is being used to create the low-loss broadband signal path design
of the spatial transformer. Mesatronic's D.O.D ("Die-On-Die") Technology