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5 4 3 2 1
D D
Compal Confidential
C
PBL10 Project C
LA-6731P REV1.0 Schematic
B B
Intel Sandy Bridge/Cougar Point(UMA)
2010-12-06 Rev 1.0
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/17 Deciphered Date 2011/05/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6731
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401968
Date: Wednesday, March 09, 2011 Sheet 1 of 45
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Compal Confidential CK505
Model Name : PBL10 Fan Control
page 5
File Name : LA-6731P Clock Generator
Mobile Sandy Bridge ICS9LRS Page 14
CPU Dual Core
D Memory BUS(DDRIII) D
Socket-rPGA989 Dual Channel 204pin DDRIII-SO-DIMM X2
1.5V DDRIII 1066/1333 BANK 0, 1, 2, 3 page 12,13
37.5mm*37.5mm page 5,6,7,8,9,10,11
DMI X4 FDI X4
LCD Conn. USB/B Right USB/B Left
page 15
USB port 0,1 USB port 2
page 29 page 29
CRT
page 16
Int. Camera RTS5138 3IN1
USB port 11 USB port 3
C
USB page 15 page 32 C
HDMI Conn. HDMI
page 17
Level Shifter
page 17
Intel Cougar Point
FCBGA989
25mm*25mm
SATA port 1 SATA HDD0
5V 1.5GHz(150MB/s) page 27
PCIeMini Card USB
WLAN & BT 2.0
SATA port 4 SATA ODD
PCIe 1x 5V 1.5GHz(150MB/s)
USB port 5 page 27
PCIe port 2 1.5V 2.5GHz(250MB/s)
page 29
SPI ROM
page 28
B B
RTL8111E Giga
RJ45 PCIe 1x
USB&Audio/B page 30
RTL8105E 10/100 1.5V 2.5GHz(250MB/s)
page 29 PCIe port 3 page 18,19,20,21 HD Audio 3.3V 24.576MHz/48Mhz
page 30 22,23,24,25,26
Power/B HDA Codec
page 34
ALC259
page 31
Touch Pad/B
page 34
ENE KB930
page 33
RTC CKT.
Int.
page 36 MIC CONN MIC CONN HP CONN SPK CONN
page 15 page 29 page 29 page 31
A
DC/DC Interface CKT. Int.KBD SPI ROM A
page 32 page 32
page 35
Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit DC/DC Issued Date 2010/05/17 Deciphered Date 2011/05/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6731
page 36,37,38,39, AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
40,41,42,43,44 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401968
Date: Wednesday, March 09, 2011 Sheet 2 of 45
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D D
POK
+3VL B+ +VSB
+5VL TP0610K
B+ +5VALW
UP6182CQAG +CPU_CORE
SUSP
+5VS ISL95831CRZ +VGFX_CORE
SI4800BDY
SYSON
+HDMI_5V_OUT
RB161M +1.5V
G5603RU1U
SUSP
+CRT_VCC
USB_EN# RB491D +1.5VS
SI4856ADY
+USB_VCCA
RT9715BGS SUSP#
USB_EN#
+1.05VS_VCCP
G5603RU1U
C C
+USB_VCCB
RT9715BGS SUSP
SUSP#
+0.75VS
UP7711U8
+1.8VS
SY8033BDBC
SUSP#
+VCCSA
G5603RU1U
+3VALW
PCH_PWR_EN#
+3VALW_PCH
SI4800BDY
SUSP
+3VS
SI4800BDY
B
VGA_ENVDD B
+LCD_VDD
AO3413
+3V_LAN
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/17 Deciphered Date 2011/05/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6731
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401968
Date: Wednesday, March 09, 2011 Sheet 3 of 45
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Voltage Rails
Power Plane Description S1 S3 S5 EC SM Bus1 address EC SM Bus2 address
VIN Adapter power supply (19V) N/A N/A N/A
Device Address Device Address
BATT+ Battery power supply (12.6V) N/A N/A N/A
Smart Battery 0001 011X b
D B+ AC or battery power rail for power circuit. N/A N/A N/A D
+CPU_CORE Core voltage for CPU ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF PCH SM Bus address
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
Device Address
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF Clock Generator (9LVS3199AKLFT, 1101 0010b
RTM890N-631-VB-GRT)
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF
DDR DIMM0 1001 000Xb
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF
DDR DIMM2 1001 010Xb
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON* BOM configu table
+3VALW_EC +3VALW always to KBC ON ON ON*
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* SKU Bom config Description
C +3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* C
1 46196830L01 DA6@/HDMI@/8105E@/PCH@ PBL10 UMA DUAL 10-100
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON* 2 46196830L02 DA6@/HDMI@/8111E@/PCH@ PBL10 UMA DUAL GIGA LAN
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
3
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* 4
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
5
6
SIGNAL 7
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
8
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW Bom configu(HDMI@/8105E@/8111E@/DA6@/DAZ@/45@)
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B
PCH And PCBA table B
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
U4
BD82HM65 SLH9D B2 FCBGA 989P PCH
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF PCH PCH@
ZZZ DAZ@ ZZZ DA6@ ZZZ DA4@ ZZZ DA2@
PCB
PCB LA-6731P REV10 PCB LA-6731P REV10 PCB LS-6732P REV10 PCB LS-6731P REV10
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/17 Deciphered Date 2011/05/17 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6731
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401968
Date: Wednesday, March 09, 2011 Sheet 4 of 45
5 4 3 2 1
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R41 1 @ 2 0_0402_5% CLK_BUF_CPU_BCLK 14
JCPUB R42 1 @ 2 0_0402_5% CLK_BUF_CPU_BCLK# 14
A28 CLK_CPU_DMI_R R43 1 2 0_0402_5% CLK_CPU_DMI 19
MISC
CLOCKS
D BCLK CLK_CPU_DMII#_R R44 D
22 H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 1 2 0_0402_5% CLK_CPU_DMI# 19
T68 PAD SKTOCC# AN34 SKTOCC#
DPLL_REF_CLK A16 R234 1 2 1K_0402_5%
H_PROCHOT# 1 2@ A15 R240 1 2 1K_0402_5% +1.05VS_VCCP
C234 0.1U_0402_16V4Z DPLL_REF_CLK#
H_THRMTRIP# 1 2@
C235 0.1U_0402_16V4Z T5 PAD H_CATERR# AL33
H_PM_SYNC @ CATERR#
1 2 DDR3 Compensation Signals
C236 0.1U_0402_16V4Z R48
THERMAL
0_0402_5%
1 2 H_PECI_ISO AN33 R8 H_DRAMRST# SM_RCOMP0 R49 2 1 140_0402_1%
23,33 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7
PM_SYS_PWRGD_BUF 1 2@
DDR3
MISC
C238 0.1U_0402_16V4Z R52 SM_RCOMP1 R51 2 1 25.5_0402_1%
BUF_CPU_RST# 1 2@ 56_0402_5%
C243 0.1U_0402_16V4Z 33 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 SM_RCOMP2 R53 2 1 200_0402_1%
PROCHOT# SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1] A5
EMI Demand R54 A4 SM_RCOMP2
0_0402_5% SM_RCOMP[2]
1 2 H_THEMTRIP#_R AN32
23 H_THRMTRIP# THERMTRIP#
PU/PD for JTAG signals +1.05VS_VCCP
XDP_TMS R55 2 1 51_0402_5%
PRDY# AP29
AP27 XDP_TDI_R R56 2 1 51_0402_5%
PREQ#
R58 AR26 XDP_TCK XDP_TDO_R R57 2 1 51_0402_5%
TCK
PWR MANAGEMENT
0_0402_5% XDP_TMS
JTAG & BPM
TMS AR27
1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST# XDP_TCK R59 2 1 51_0402_5%
20 H_PM_SYNC PM_SYNC TRST#
C R64 XDP_TDI_R XDP_TRST# R62 C
TDI AR28 2 1 51_0402_5%
0_0402_5% AP26 XDP_TDO_R
H_CPUPWRGD_R TDO
23 H_CPUPWRGD 1 2 AP33 UNCOREPWRGOOD
R65
130_0402_5% AL35 R266 1K_0402_5%
+1.05VS_VCCP PM_SYS_PWRGD_BUF 1 DBR#
Processor Pullups 2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK 1 2 +3VS
AT28 XDP_DBRESET# XDP_DBRESET# 18,20
R47 BPM#[0]
2 1 62_0402_5% H_PROCHOT#
BPM#[1] AR29
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30
RESET# BPM#[3]
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
2 1 H_CPUPWRGD_R
R50 10K_0402_5%
1 2
C312 330P_0402_50V7K Sandy Bridge_rPGA_Rev1p0
@ CLOSE TO PCH, EMI DEMAND CONN@
+3VS Buffered reset to CPU
+1.05VS_VCCP
1
C82
B 0.1U_0402_16V4Z B
1
2 R60
75_0402_5% FAN Control Circuit
5
U2 R66 +5VS
2
1 43_0402_1%
P
NC BUFO_CPU_RST#
Y 4 1 2 BUF_CPU_RST# 1A
PLT_RST# 2
A
G
1
SN74LVC1G07DCKR_SC70-5
@
3
R68
0_0402_5% 2
2
C863 JFAN
PLT_RST# 22,29,30,33
10U_0805_10V4Z +FAN1 1
1 1
2 2
2 3 3
U58
1 8 @ C864
@C864 4
+3VALW EN GND 1000P_0402_50V7K GND
Follow DG 0.71 +FAN1
2 VIN GND 7
1
5 GND
3 VOUT GND 6
33 EN_DFAN1 4 VSET GND 5 ACES_85205-03001
+1.5V_CPU_VDDQ
1 1
C83 10mil G996P11U SOP 8P CONN@
0.1U_0402_16V4Z C17
1
10U_0805_10V4Z R219 10K_0402_5%
2 U3 R81 2
2 1 +3VS
R82 74AHC1G09GW_TSSOP5 200_0402_5%
5
0_0402_5% FAN_SPEED1 33
1 2 1 1
P
20 SYS_PWROK
2
B PM_SYS_PWRGD_BUF
O 4
A C865@ A
20 PM_DRAM_PWRGD 2 A
G
0.01U_0402_25V7K
2