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Schematic Diagrams

System Block Diagram
VDD3,VDD5
W150HRM/W170HR Huron River System Block Diagram W150HRM 7IN1 6-7P-W15R7-002
W150HRM MAIN BOARD
GPU NVDIDA N12x NVVDD 6-71-W15H0-D02

PCIE*8 AUDIO BOARD
5V,3V,5VS,3VS,1.5VS, PHONE JACK x3, USB x1
1.8VS,+1.5S_CPU Sandy Bridge RJ-11 6-71-W150A-D02

Nvidia 800/1067/1333 MHz SECOND HDD/ODD BOARD
1.8V, PEX_VDD,0.85VS PROCESSOR DDR3 / 1.5V 6-71-W150N-D01
Fermi N12E-GE-A1 DDRIII
rPGA988B SO-DIMM2 FINGER PRINTER BOARD
RAM SIZE:2GB SHEET 10 6-71-B510F-D02
1.5V,0.75VS(VTT_MEM)
FBVDDQ (128MX16) SYSTEM SMBUS DDRIII
1005 Balls 0.1"~13 CLICK BOARD
SO-DIMM1
B.Schematic Diagrams

FDI DMI*4 6-71-B5102-D04
SHEET 9
1.05VS_VTT 0.5"~5.5" <=8" AUDIO BOARD POWER SWITCH BOARD
6-71-B510S-D03
<8" W150HNM
LCD CONNECTOR
CRT CONNECTOR <15" INT SPKER-R
VGFX_CORE SPDIF MIC HP LED & VGA S/W BOARD
OUT IN OUT 6-71-B5134-D01

Sheet 1 of 49 HDMI Connector CougarPoint USB PORT (USB8) W170HR 8IN1 6-7P-W1708-001
W150HNM (INT SPK R)
System Block SENTELIC 10
6-49-C4102-0
TOUCHBOARD
Controller W150HN MAIN BOARD
6-71-W1500-D01
CLICK PAD SPI Hub (PCH)
Diagram TPM 1.2 W150HNM AUDIO BOARD
Optional PHONE JACK x3, USB x1
IN SPK
T ER-L
32.768 KHz Azalia Codec RJ-11 6-71-W170A-D01
EC LPC 27x27mm REALTAK
ITE 8518E 33 MHz 989 Ball FCBGA ALC269 SECOND HDD/ODD BOARD
0.5"~11" 6-71-W170N-D01
128pins LQFP
14 *1 4*1 .6m m INT MIC K/B TRANSFER BOARD
BIOS 6-71-B7117-D01
SPI 24 MHz AZALIA LINK
INT. K/B
EC SMBUS CLICK BOARD
25 6-71-B7112-D02
PCIE 100 MHz <12" MHz
THERMAL SMART SMART POWER SWITCH BOARD
SENSOR FAN BATTERY 6-71-B711S-D02
W83L771AWG AC-IN 32.768KHz
Mini PCIE Mini PCIE JMICRO LED & VGA S/W BOARD
SOCKET SOCKET JMC251_C 6-71-B7134-D01
SATA I/II 3.0Gb/s USB2.0 3G MSATA CARD WLAN CARD
<12" (USB2/SATA3) (USB2) DEBUG BOARD
USB3.0 LAN READER 6-71-W840TD-D03
480 Mbps VLI8012 (Optional)
1"~16" *NEC uPD720200

B5100 RJ-45 7IN1
SATA HDD SATA ODD eSATA SOCKET
(B4100M) USB PORT1 CCD FINGER PRINTER BOARD
(USB0) (USB5)
(USB4)
FingerPrint USB PORT2 USB PORT3

W150HNM (Optional) 12 MHz
SECOND HDD BOARD
USB3.0

B - 2 System Block Diagram

http://hobi-elektronika.net
Schematic Diagrams

Sandy Bridge Processor 1/7
Sandy Bridge Processor 1/7 ( DMI,PEG,FDI )
1 . 05 V S _ V T T

CPU U4 9 A
J22 20 mil P E G_ I R C O M P _ R R1 3 3 2 4 . 9 _ 1% _ 0 4
P E G _ I C O MP I J21
B2 7 P E G_ I C OM P O H 22
20 DM I_ T X N0 B2 5 DM I_ RX # [0 ] P E G _ R C OM P O
H1 6 H 15 H 8
H 8 _ 0 D 4 _ 4 H 8 _0 D 4 _4 H 8 _ 0D 4 _ 4 20 DM I_ T X N1 A2 5 DM I_ RX # [1 ]
20 DM I_ T X N2 B2 4 DM I_ RX # [2 ] K3 3
20 DM I_ T X N3 DM I_ RX # [3 ] PE G _ RX# [0 ] PE G_ R X# 0 12
M 35
PE G _ RX# [1 ] PE G_ R X# 1 12
B2 8 L34
20 DM I_ T X P 0 B2 6 DM I_ RX [0 ] PE G _ RX# [2 ] J35 PE G_ R X# 2 12
20 DM I_ T X P 1 DM I_ RX [1 ] PE G _ RX# [3 ] PE G_ R X# 3 12
A2 4 J32
20 DM I_ T X P 2 DM I_ RX [2 ] PE G _ RX# [4 ] PE G_ R X# 4 12
B2 3 H 34

DMI
20 DM I_ T X P 3 DM I_ RX [3 ] PE G _ RX# [5 ] H 31 PE G_ R X# 5 12
PE G _ RX# [6 ] PE G_ R X# 6 12
G 21 G 33
20 DM I_ RX N 0 DM I _ T X# [ 0 ] PE G _ RX# [7 ] PE G_ R X# 7 12
E2 2 G 30
20 DM I_ RX N 1 F21 DM I _ T X# [ 1 ] PE G _ RX# [8 ] F35
20 DM I_ RX N 2 D 21 DM I _ T X# [ 2 ] PE G _ RX# [9 ] E3 4
20 DM I_ RX N 3 DM I _ T X# [ 3 ] P E G _ RX # [1 0 ] E3 2
G 22 P E G _ RX # [1 1 ] D 33

B.Schematic Diagrams
20 DM I_ RX P 0 D 22 DM I _ T X[ 0] P E G _ RX # [1 2 ] D 31
20 DM I_ RX P 1
F20 DM I _ T X[ 1] P E G _ RX # [1 3 ] B3 3
PEG Compensation Signal
20 DM I_ RX P 2 C 21 DM I _ T X[ 2] P E G _ RX # [1 4 ] C 32
20 DM I_ RX P 3 DM I _ T X[ 3] P E G _ RX # [1 5 ]

PCI EXPRESS* - GRAPHICS
J33
CAD NOTE: PEG_ICOMPI and RCOMPO signals
P E G _R X [ 0 ] L35 PE G_ R X0 12 should be shorted and routed with
P E G _R X [ 1 ] PE G_ R X1 12
K3 4
A2 1 P E G _R X [ 2 ] H 35
PE G_ R X2 12 - max length = 500 mils
20 F DI_ T X N0 H 19 FD I 0_ T X # [ 0 ] P E G _R X [ 3 ] H 32 PE G_ R X3 12
20 F DI_ T X N1 FD I 0_ T X # [ 1 ] P E G _R X [ 4 ] PE G_ R X4 12 - typical impedance = 43 mohms
E1 9 G 34
20 F DI_ T X N2 FD I 0_ T X # [ 2 ] P E G _R X [ 5 ] PE G_ R X5 12 PEG_ICOMPO signals should be routed with
F18 G 31
20 F DI_ T X N3 B2 1 FD I 0_ T X # [ 3 ] P E G _R X [ 6 ] F33 PE G_ R X6 12
PE G_ R X7 12 - max length = 500 mils

Intel(R ) FDI
20 F DI_ T X N4 C 20 FD I 1_ T X # [ 0 ] P E G _R X [ 7 ] F30
20 F DI_ T X N5 FD I 1_ T X # [ 1 ] P E G _R X [ 8 ]
20 F DI_ T X N6
D 18
FD I 1_ T X # [ 2 ] P E G _R X [ 9 ]
E3 5 - typical impedance = 14.5 mohms
E1 7 E3 3
20 F DI_ T X N7 FD I 1_ T X # [ 3 ] PE G _ RX[1 0 ] F32

20
20
F DI_ T X P 0
F DI_ T X P 1
A2 2
G 19 FD I 0_ T X [ 0 ]
PE G _ RX[1 1 ]
PE G _ RX[1 2 ]
PE G _ RX[1 3 ]
D 34
E3 1
C 33
Sheet 2 of 49
E2 0 FD I 0_ T X [ 1 ] PE G _ RX[1 4 ] B3 2
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and route with
d
20
20
20
F DI_ T X P 2
F DI_ T X P 3
F DI_ T X P 4
G 18
B2 0
C 19
FD
FD
FD
I 0_ T X [ 2 ]
I 0_ T X [ 3 ]
I 1_ T X [ 0 ]
PE G _ RX[1 5 ]

P E G_ T X # [ 0 ]
M 29
M 32
PE
PE
G_ T X # _0
G_ T X # _1
C
C
591
589
0.
0.
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
_ 04
_ 04
PE G_ T X #0 12
Sandy Bridge
- typical impedance < 25 mohms 20 F DI_ T X P 5 D 19 FD I 1_ T X [ 1 ] P E G_ T X # [ 1 ] M 31 PE G_ T X #1 12

1. 05 V S _V TT 1 .0 5 V S_ VT T
20
20
F DI_ T X P 6
F DI_ T X P 7
F17

J18
FD
FD
I 1_ T X [ 2 ]
I 1_ T X [ 3 ]
P E G_ T X # [ 2 ]
P E G_ T X # [ 3 ]
P E G_ T X # [ 4 ]
L32
L29
K3 1
PE
PE
PE
PE
G_ T X # _2
G_ T X # _3
G_ T X # _4
G_ T X # _5
C
C
C
C
594
596
598
601
0.
0.
0.
0.
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
_ 04
_ 04
_ 04
_ 04
PE
PE
PE
G_ T X #2
G_ T X #3
G_ T X #4
12
12
12
Processor 1/7
20 F D I_ F S Y N C 0 J17 F D I 0_ F S Y N C P E G_ T X # [ 5 ] K2 8 PE G_ T X # _6 PE G_ T X #5 12
C 606 0. 22 u _ 1 0 V _ X5 R _ 04 PE G_ T X #6 12
20 F D I_ F S Y N C 1 F D I 1_ F S Y N C P E G_ T X # [ 6 ] J30 PE G_ T X # _7 C 608 0. 22 u _ 1 0 V _ X5 R _ 04
H 20 P E G_ T X # [ 7 ] J28 PE G_ T X #7 12
20 F D I_ INT F D I _I N T P E G_ T X # [ 8 ] H 29
J19 P E G_ T X # [ 9 ] G 27
20 F D I _ LS Y N C 0 H 17 F D I 0_ L S Y N C P E G _T X # [ 1 0 ] E2 9
R 521 R5 1 9
20 F D I _ LS Y N C 1 F D I 1_ L S Y N C P E G _T X # [ 1 1 ] F27
1 K_ 1 % _ 0 4 2 4 . 9_ 1 % _ 0 4
P E G _T X # [ 1 2 ] D 28
ED P H P D Fu nc ti o n D is ab l e P E G _T X # [ 1 3 ] F26
ED P_ HP D : Pu ll -u p 10 K- D IS A BL ED H PD P E G _T X # [ 1 4 ] E2 5
E D P _ C OM P I O A1 8 P E G _T X # [ 1 5 ]
A1 7 e D P _ C OM P I O M 28
DP Compensation Signal PE G_ T X _ 0 C 587 0.