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1 2 3 4 5 6 7 8
01
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND1
ZG8 Block Diagram
LAYER 3 : IN1
LAYER 4 : IN2
A LAYER 5 : VCC A
Intel Diamondville
LAYER 6 : IN3
LAYER 7 : GND2 FSB P3,4
LAYER 8 : BOT
FSB(533/667MHZ)
FSB INT_CRT
DDR SYSTEM MEMORY
1.8@ for 1.8HDD Channel A DDR II CRT
Graphics Interfaces
533 MHZ P14
DDRII-SODIMM Intel 945GMS
2.5@ for 2.5HDD
P13
NB
P5,6,7,8,9 INT_LVDS
10.1"Panel
DMI P14
DMI(x2)
B B
SATA 0 DMI
SATA - HDD SATA PCIE-1
P19
USB-5 3G/WiMAX SIM Card
P20
CK505
PCI-Express
PCI-E P2
PCIE-2
10/100 LAN POWER SYSTEM
Intel I/O Controller Hub 7 ISL88731 P24
Atheros 8132/8114 P18
(ICH7M) ISL6237 P25
USB-0 USB 2.0 (Port0~7)
CCD ISL6261A P26
USB
P14 TPS51116 P27
SB PCIE-3
G9338 P29
P10,11,12 WLAN RT8202 P30
USB-6
P20
4 in 1 Card Reader USB-3
Realtek RTS5159 P21 RTC
VCC_CORE
C C
USB-1,2,4
USB port*3 BATTERY PCIE-4 SD Cardreader
P17
P24 JM385 +1.5V
P22
USB-7
Bluetooth module Azalia
P15
IHDA +1.05V
LPC
+1.8VSUS
LPC
+1.5VVSUS
Audio Codec EC Winbond WPCE775L +2.5V
Realtek ALC272 3VPCU
P16 P23 +3.3V
+3.3VSUS
LCD_3.3V
Touch Pad /B LCD_5V
K/B Con. SPI Flash Charger +5V
om
D
Con. D
Audio AMP P15 P15 P23 P24 +SMDDR_VTERM
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P16 +SMDDR_VREF
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Quanta Computer Inc.
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Int. MIC Audio Jack Int. SPK
PROJECT : ZG8
in
Size Document Number Rev
xa
Block Diagram 1A
he
Date: Monday, January 19, 2009 Sheet 1 of 33
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator(CLK) +3V
02
+1.05V_VDD PM_STPPCI# R114 2.2K_4
PBY160808T-301Y-N/2A/300ohm_6
+3V C190 L12 +1.05V
L13 *0.1u/10V_4 PBY160808T-301Y-N/2A/300ohm_6 PM_STPCPU# R113 2.2K_4
C199 C171 C179 C187 C177 C172 C173 C178 C176
*0.1u/10V_4
C168 *10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 NEW_CLKREQ#_R R110 10K_4
*10u/10V_8
D C182 U2 D
0.1u/10V_4 9 55 SATA_CLKREQ#_R R132 10K_4
C194 16
VDD_PCI IO_VOUT 0121 Add
0.1u/10V_4 VDD_48 SMBCK1
23 VDD_PLL3 SCLK 7
C184 VDD_CK_VDD_REF 4 6 SMBDT1 PCLK_591_R C196 *33p/50V_4
0.1u/10V_4 VDD_REF SDA
C170
CK505 PM_STPPCI#
46 VDD_SRC SRC5/PCI_STOP# 45 PM_STPPCI# (12)
0.1u/10V_4 62 44 PM_STPCPU# PM_STPCPU# (12) To SB CLKUSB_48 C197 *15p/50V_4
VDD_CPU SRC5#/CPU_STOP#
+1.05V_VDD
C208 19 61
VDD_96_IO CPU0 CLK_CPU_BCLK (3)
27 60 To CPU 14M_ICH C214 *33p/50V_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (3)
10u/10V_8 33 VDD_SRC_IO_1
52 VDD_SRC_IO_3 CPU1 58 CLK_MCH_BCLK (5)
43 57 To NB PCLK_ICH_R C193 *33p/50V_4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# (5)
56 VDD_CPU_IO
54 T20
0121 Add SRC8/ITP
53 T19
SRC8#/ITP#
R129 475/F_4 SATA_CLKREQ#_R 8 42
(20)
SATA_CLKREQ# PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# (7)
SRC10 41 CLK_PCIE_3GPLL (7) To NB
R157 47_4 PCLK_DEBUG_R 10
(20) PCLK_DEBUG PCI1/CR#_B
40 CLK_MCH_OE#_R R112 475/F_4 MCH_CLKREQ# (7)
PCLK_OZ129 SRC11/CR#_H NEW_CLKREQ#_R R111 475/F_4
11 PCI2/TME SRC11#/CR#_G 39 CLKREQ_WLAN# (20)
T67 PCI_CLK_SIO 12 37
PCI3 SRC9 PE2CLK+ (20)
C SRC9# 38 PE2CLK- (20) To Mini Card 1 (WLAN) C
R160 33_4 PCLK_591_R 13
(23) LCLK_EC PCI4/SRC5_EN
SRC7/CR#_F 51 PE1CLK+ (18)
PCLK_ICH R153 33_4 PCLK_ICH_R 14 50 To LAN
(11) PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E PE1CLK- (18)
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48
XTAL_IN SRC6 PE0CLK+ (20)
SRC6# 47 PE0CLK- (20) To Mini Card 2 (3G/WMAX) FSC FSB FSA CPU SRC PCI
CG_XOUT 2
R144 22_4 XTAL_OUT
(21) CLK_Card48_1 R147 22_4 FSA SRC4 34 PE3CLK+ (22) 1 0 1 100 100 33
(12) CLKUSB_48
17 USB_48/FSA SRC4# 35 PE3CLK- (22) To SDIO
CLK_BSEL0 R140 2.2K_4 0 0 1 133 100 33 Default
CLK_BSEL1 64 31
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH (11)
CLK_BSEL2 R158 10K_4 32 To SB 0 1 1 166 100 33
SRC3#/CR#_D CLK_PCIE_ICH# (11)
R156 47_4 FSC 5
(12) 14M_ICH REF0/FSC/TESTSEL
65 VSS_BODY SRC2/SATA 28 CLK_PCIE_SATA (10) 0 1 0 200 100 33
15 VSS_PCI SRC2#/SATA# 29 CLK_PCIE_SATA# (10) To SB
C201 18 0 0 0 266 100 33
33p/50V_4 CG_XIN VSS_48
22 VSS_IO SRC1/SE1 24 DREFSSCLK (7)
26 VSS_PLL3 SRC1#/SE2 25 DREFSSCLK# (7) To NB 1 0 0 333 100 33
2
Y2 59
CL=20p VSS_CPU
14.318MHZ
30 VSS_SRC1 SRC0/DOT96 20 DREFCLK (7) 1 1 0 400 100 33
36 VSS_SRC2 SRC0#/DOT96# 21 DREFCLK# (7) To NB
C202 49 1 1 1 Reserved
1
33p/50V_4 CG_XOUT VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK410 (12)
B SLG8SP513 B
SLG8SP513VTR ,ICS9LPRS365BKLFT
12/19 modify +3V R167 10K_4 PCLK_OZ129 To NB
ICS9LPRS365 RTM875T-606 CLK_BSEL0 R128 1K_4
(ALPRS365K13) (AL000875K06) (3) CPU_BSEL0 MCH_BSEL0 (7)
PULL HIGH PULL DOWN R168 *10K_4
PCI2/TME
Pin 11 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN
+3V R161 *10K_4 PCLK_591_R
PCI-3/SRC5_EN PIN37/38 IS HIGH 27MHz
Pin 12 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) LOW SRC CLK_BSEL1 R145 1K_4
(3) CPU_BSEL1 MCH_BSEL1 (7)
R155 10K_4
PCI-4/27M_SEL PIN 17/18
Pin 13 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default)
+3V R151 *10K_4 PCLK_ICH_R
PCIF-5/ITP_EN
Pin 14 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default)
R152 10K_4 CLK_BSEL2 R146 1K_4
(3) CPU_BSEL2 MCH_BSEL2 (7)
+3V :ICS9LPRS365BGLFT QCI:ALPRS365K13 +3V
Clock Gen I2C :SLG8SP512TTR: QCI:AL8SP512K05
A A
R172 R171
4.7K_4 4.7K_4
2
2
Q8 Q7
(12,20) PDAT_SMB 3 1 SMBDT1
SMBDT1 (13) (12,20) PCLK_SMB 3 1 SMBCK1
SMBCK1 (13)
Quanta Computer Inc.
2N7002E 2N7002E PROJECT : ZG8
Size Document Number Rev
1A
CLOCK GENERATOR
Date: Tuesday, February 03, 2009 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
CPU-1(CPU) U21A U21B 03
(5) H_A#[31:3] H_A#3 (5) H_D#[63:0] H_D#0 H_D#32 H_D#[63:0] (5)
P21 A[3]# ADS# V19 H_ADS# (5) Y11 D[0]# D[32]# R3
H_A#4 H20 Y19 H_D#1 W10 R2 H_D#33
H_A#5 A[4]# BNR# H_BNR# (5) H_D#2 D[1]# D[33]# H_D#34
N20 U21 H_BPRI# (5) Y12 P1
H_A#6 A[5]# BPRI# H_D#3 D[2]# D[34]# H_D#35
R20 AA14 N1
A[6]# D[3]# D[35]#
0
GROUP
ADDR
DATA GRP 0
DATA GRP 0
H_A#7 J19 T21 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# (5) D[4]# D[36]#
H_A#8 N19 T19 H_D#5 W12 P2 H_D#37
H_A#9 A[8]# DRDY# H_DRDY# (5) H_D#6 D[5]# D[37]# H_D#38
G20 Y18 H_DBSY# (5) AA16 J3
DATA GRP 2
H_A#10 A[9]# DBSY# H_D#7 D[6]# D[38]# H_D#39
D M19 A[10]# Y10 D[7]# D[39]# N3 D
H_A#11 H21 T20 H_D#8 Y9 G3 H_D#40
H_A#12 A[11]# BR0# H_BREQ#0 (5) H_D#9 D[8]# D[40]# H_D#41
L20 A[12]# Y13 D[9]# D[41]# H2
CONTROL
H_A#13 M20 F16 IERR# R176 56_4 +1.05V H_D#10 W15 N2 H_D#42
H_A#14 A[13]# IERR# H_INIT#R R116 H_D#11 D[10]# D[42]# H_D#43
K19 A[14]# INIT# V16 H_INIT# (10) AA13 D[11]# D[43]# L2
H_A#15 J20 1K/F_4 R115 330_4 H_D#12 Y16 M3 H_D#44
A[15]# +1.05V D[12]# D[44]#
H_A#16 L21 W20 H_D#13 W13 J2 H_D#45
A[16]# LOCK# H_LOCK# (5) H_D#14 D[13]# D[45]# H_D#46
(5) H_ADSTB#0 K20 ADSTB[0]# H_CPURST# (5) AA9 D[14]# D[46]# H1
T37 H_AP0 D17 D15 H_D#15 W9 J1 H_D#47
(5) H_REQ#[4:0] H_REQ#0 N21 AP0 RESET# H_RS#[2:0] (5) D[15]# D[47]#
W18 H_RS#0 (5) H_DSTBN#0 Y14 K2 H_DSTBN#2 (5)
H_REQ#1 J21 REQ[0]# RS[0]# DSTBN[0]# DSTBN[2]#
Y17 H_RS#1 (5) H_DSTBP#0 Y15 K3 H_DSTBP#2 (5)
H_REQ#2 G19 REQ[1]# RS[1]# DSTBP[0]# DSTBP[2]#
U20 H_RS#2 (5) H_DINV#0 W16 L1 H_DINV#2 (5)
H_REQ#3 P20 REQ[2]# RS[2]# T18 H_DP#0 DINV[0]# DINV[2]# H_DP#2 T30
W19 H_TRDY# (5) V9 M4
H_REQ#4 R19 REQ[3]# TRDY# DP#0 DP#2
REQ[4]# (5) H_D#[63:0] H_D#16 H_D#48 H_D#[63:0] (5)
(5) H_A#[31:3] AA17 H_HIT# (5) AA5 C2
H_A#17 HIT# H_D#17 D[16]# D[48]# H_D#49
C19 V20 H_HITM# (5) Y8 G2
H_A#18 A[17]# HITM# H_D#18 D[17]# D[49]# H_D#50
F19 W3 F1
H_A#19 A[18]# XDP_BPM#0 T28 H_D#19 D[18]# D[50]# H_D#51
E21 K17 U1 D3
H_A#20 A[19]# BPM[0]# XDP_BPM#1 T31 H_D#20 D[19]# D[51]# H_D#52
A16 J18 W7 B4
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
DATA GRP 1
H_A#21 D19 H15 XDP_BPM#2 T35 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# XDP_BPM#3 T34 H_D#22 D[21]# D[53]# H_D#54
C14 J15 Y7 A5
A[22]# BPM[3]# D[22]# D[54]#
ADDR GROUP 1
H_A#23 XDP_BPM#4 T32 H_D#23 H_D#55
DATA GRP 3
C18 K18 AA6 C3
XDP/ITP SIGNALS
C H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56 C
C20 J16 Y3 A6
H_A#25 A[24]# PREQ# XDP_TCK H_D#25 D[24]# D[56]# H_D#57
E20 M17 W2 F2
H_A#26 A[25]# TCK XDP_TDI H_D#26 D[25]# D[57]# H_D#58
D20 N16 V3 C6
H_A#27 A[26]# TDI XDP_TDO T27 H_D#27 D[26]# D[58]#