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5 4 3 2 1

S04
BLOCK DIAGRAM DC/DC & Charger
Dothan(Yonah)/Alviso
D D

CPU VR Switching
MAX1987 P:31 +VCCP,1.5V MAX1715 P:36
3V,5V MAX1999 P:33
+1.8V VCORE_CPU +3V
+1.5V AC/BATT VGA CORE MAX1993 P:35
Dothan/Yonah +3V Clocks Connector P:39 VDIMM,VTT_MEM MAX8550 P:34
CK410
478 Pins CPU Thermal CYPRESS: CY28411
hocnghetructuyen.vn RTC
Sensor LDO
(Micro-FCPGA) IDT CV125 Battery P:33
MAX6648 P:5 P:4 1.2V(ATI) MAX8527 P:37
+1.8V L1087_ADJ P:37
+VCCP P:5,6
LVDS LCD Panel
FSB VCORE_VGA
P:25 +2.5V P:37
4X100MHZ Video Controller
C 4X133MHZ +1.5VATI-M24CSP R.G,B CRT port C
VTT_MEM VDIMM PCI-Express x16(GFX) +1.8V
+1.2V P:24
DDR-SODIMM1 DDR SDRAM 2.5V, 400/500MHz +VCCP(1.05V) +1.5V +2.5V
S-VIDEO +5V +3V
P:12 +3V P:21,22,23 +3VSUS
( 915PM ) P:24
VDIMM(2.5V) MINI-PCI
Alviso
DDR-SODIMM2 DDR SDRAM 2.5V, 400/500MHz 1257 PCBGA PIRQCJ,DJ Intel
P:13 AD20 Calexico II
+2.5V +3V REQ1J P:20
P:7,8,9,10,11
Primary IDE - HDD DMI 33MHZ, 3.3V PCI
+5V 33MHZ, 3.3V PCI
Master P:17 CON CON
VCCRTC +1.5VSUS
+5V
DVD/CDRW/CD/COMBO ATA 66/100 +VCCP(1.05V) +3V PCI-Express x1 AD25 AD23 AD22
Sl ave P:17 PIRQEJ PIRQBJ REQ2J PIRQAJ
ICH6-M P:38 P:1 REQ3J REQ0J
B
AC-LINK
+2.5V
+1.5V 609 BGA USB 2.0 +1.5V +3V +3V +3VAUX
B

+5V +3VSUS +3V 3VAUX
Headphone +3V CardBus
+5VSUS NewCard
P:27 +3VSUS
CardReader 1394 LAN
P:14,15,16 P:5 P:5 OZ711 VT6307 10/100/1G
+5V +3V +5V +3VAUX
USB PORT -->2,6 P:5 P:4 RTL8110S-32
External AUDIO MDC1.0 +5VSUS P:17
RJ11 USB --> 7 USB -->0
MIC P:27 ALC202A(Codec) +3V P:20 P:2
TPA0312(Amp)
P:26
CON P:38 SD&MMC&MS CARD 1394
Internal Slot BUS CONN
RJ45
P:3
MIC P:1 +5V
+3V
+3VALW VCCRTC SLOT

PC87591
PCI Board CON PCI Board RJ11
176 Pins LQFP
A P:28 A

+5V +5V +3VALW +5V USB --> 1
+5VSUS TECHNOLOGY COPR.
Touchpad Keyboard FLASH FAN 1 Title
P:29 P:29 P:28 P:30 USB BOARD BLOCK DIAGRAM
Document Number R ev

S04 MAINBOARD A
Date: Monday, June 14, 2004 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1

Power & Ground
Label Pg# S0 S3 S4 S5 Control Signal
MBATA+
MBATA+ 39 Y Y Y Y 9V-12.6V,3X2 cells
VIN
VIN 25,31,33,34,35,36,39 Y Y Y Y 20V-9V

D VCCRTC
VCCRTC 14,16,28,33 Y Y Y Y 3V D

+3VALW
+3VALW 19,25,28,29,33,39 Y Y Y Y 3VAUXEN hocnghetructuyen.vn
+5VALW 3VAUXEN
+5VALW 32,33 Y Y Y Y
3VAUX 3VAUXEN
3VAUX 20,33,38 Y Y Y
+1.5VSUS SUSD
+1.5VSUS 16,36,37 Y Y
VDIMM SUSON
VDIMM 7,9,10,12,13,34,37 Y Y
+3VSUS SUSD
+3VSUS 15,16,19,20,32,33,34,35 Y Y
+5VSUS SUSD
+5VSUS 16,17,32,33,36,38 Y Y
+1.5V MAIND
+1.5V 6,10,11,15,16,23,32,36,37,38 Y
+1.8V +3V
C +1.8V 6,22,23,32,37
Y C

VCORE_VGA MAIND
VCORE_VGA 23,35 Y
VMEM_VGA +1.8V
VMEM_VGA 22,23 Y
+3V MAIND
+3V 4,5,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,28,29,30,31,32,33,35,37,38 Y
+5V MAIND
+5V 16,17,20,24,25,26,27,28,29,30,31,32,33,38 Y
+5VA +5V
+5VA 26 Y
+5VAA +5V
+5VAA 26,27 Y
+5V_FAN VFAN,+5V
+5V_FAN 30 Y
M_VREF MAINON
M_VREF 7,12,13,34 Y
VCORE_CPU VRON
B VCORE_CPU 6,31 Y B

+VCCP VRON
+VCCP 4,5,6,7,9,10,14,16,36 Y
+1.2V MAIND
+1.2V 23,37 Y
+2.5V MAIND
+2.5V 7,8,10,11,16,23,32,37 Y
5VAUX 3VAUXEN
5VAUX 33,34,35,36,38 Y Y Y
VTT_MEM MAINON
VTT_MEM 12,13,34 Y
MOSVCC 5VAUX
MOSVCC 32,33 Y Y Y
MOSVCC_RUN
MOSVCC_RUN 25,30,32,33,38 Y MAINON

GND ALL PAGES
AUDGND 26,27,38
A A

AUDGND

TECHNOLOGY COPR.
Title
Frontpage
Document Number R ev

S04 MAINBOARD A
Date: Monday, June 14, 2004 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1

PWR_LED STATUS WAKE UP EVENT
S0 S1&S3 S4&S5 WAKE UP EVENT FROM ACPI STATE COMMENTS
PWR_LED ON Blinking OFF POWER BUTTON S1,S3,*S4,S5 Default set all support by BIOS
D RTC ALARM S5 Default set all support by BIOS D

LAN (PCI LAN) S1,S3,*S4 *S4 support set by BIOS,or not support

LAN LED STATUS USB S1,S3 S3 set by BIOS,or not support
TOUCH PAD/INTERNAL KB S1,S3 Default support
Green Amber Yellow
MODEM WAKEUP S3 Default support
10M/100M Blinking OFF ON
not support
1394
1000M Blinking Blinking ON
WIRELESS LAN not support

hocnghetructuyen.vn
C C

B B

A A

TECHNOLOGY COPR.
Title
Table of contects
Document Number R ev

S04 MAINBOARD A
Date: Monday, June 14, 2004 Sheet 3 of 40
5 4 3 2 1
5 4 3 2 1

CLK_MCH_BCLK R1 49.9 +/-1% R0402
CLK_MCH_BCLKJR2 49.9 +/-1% R0402
hocnghetructuyen.vn +V3.3S_CLKVDD1 CLK_CPU_BCLK R3
CLK_CPU_BCLKJ R4
49.9 +/-1%
49.9 +/-1%
R0402
R0402
CLK_NEWCARD R5 49.9 +/-1% R0402
CLK_NEWCARDJ R6 49.9 +/-1% R0402
CLK_PCIE_VGA R7 49.9 +/-1% R0402
R9 R10 CLK_PCIE_VGAJ R8 49.9 +/-1% R0402
2.2 1 CLK_PCIE_ICH R13 49.9 +/-1% R0402
+/-5% +/-5% CLK_PCIE_ICHJ R14 49.9 +/-1% R0402
R0603 R0603 CLK_PCIE_MCH R17 49.9 +/-1% R0402
D FB1 CLK_PCIE_MCHJ R18 49.9 +/-1% R0402 D
+3V FB L0805 180 Ohm DREFCLK R838 49.9 +/-1% R0402 @GM
2 1 +V3.3S_CLKVDD1 DREFCLKJ R839 49.9 +/-1% R0402
CLK_PWR
* BC1
47nF * BC2
10uF
U1
DREFssCLKJ
DREFssCLK
R949
R948
49.9 +/-1% R0402
49.9 +/-1% R0402 @GM
C0603 C0805
* BC3
47nF * BC4
10uF
1 11 C0603 C0805
VDD_PCI0 VDD_48
7 VDD_PCI1
+3V FB2 48 BC5 47nF R957 R958
VDD_REF

*
FB L0805 180 Ohm VCC3_CLK C0603 0 0
2 1 21 54 +/-5% +/-5%
VDD_SRC0 CPU_STOP# STP_CPUJ 15
28 55 R0402 R0402
VDD_SRC1 PCI_STOP# STP_PCIJ 15
* BC6
0.1uF* BC7
0.1uF * BC8
*
0.1uF
BC9
0.1uF
R20
2.2
34 VDD_SRC2
CPU1 41 R21 33 +/-5% R0402
CLK_MCH_BCLK 7
@M24 @M24

C0402 C0402 C0402 C0402 +/-5% 42 40 R23 33 +/-5% R0402
VDD_CPU CPU1# CLK_MCH_BCLKJ 7
R0603 +1.5V +1.5V
CLK_VDD_A 37 44 R24 33 +/-5% R0402
VDD_A CPU0 CLK_CPU_BCLK 5
43 R25 33 +/-5% R0402
CPU0# CLK_CPU_BCLKJ 5
* BC10
47nF * BC11
10uF
38 VSS_A
CPU_2_ITP/SRC_7 36
CLK_XTAL_OUT C0603 C0805 CLK_XTAL_OUT 49 35
CLK_XTAL_IN 50 XTAL_OUT CPU2_ITP/SRC7#
XTAL_IN R27 33 +/-5% R0402
SRC6 33 CLK_NEWCARD 38
BSEL0 53 32 R28 33 +/-5% R0402
FSC/TEST_SEL SRC6# CLK_NEWCARDJ 38
BSEL1 16
CLK_XTAL_IN FSB/TEST_MODE R29 33 +/-5% R0402
C 2 1 SRC5 31 CLK_PCIE_VGA 21 C
R30 33 +/-5% R0402 FSA 12 30 R31 33 +/-5% R0402
15 CLK48_USB FSA/USB_48 SRC5# CLK_PCIE_VGAJ 21
X1
XTAL-14.318MHz R32 33 +/-5% R0402 26
38 PCLK_1394 SRC4_SATA BC12 10pF PCLK_MINI
3 PCI3 SRC4_SATA# 27

*
R36 33 +/-5% R0402 4 C0603 50V, NPO, +/-5%
20 PCLK_MINI R38 33 +/-5% R0402 PCI4 R39 33 +/-5% R0402
28 PCLK_591 5 PCI5 SRC3 24 CLK_PCIE_ICH 15
* BC13
33pF * BC14
33pF
38 PCLK_LAN
R42 33 +/-5% R0402
56
9
PCI2
PCIF1
SRC3# 25 R41 33 +/-5% R0402
CLK_PCIE_ICHJ 15
+3V R37 10K PCIF0
C0603 C0603 R43 33 +/-5% R0402 100_96_sel 8 22 +/-5% R0402
38 PCLK_OZ R45 33 +/-5% R0402 PCIF0 PCIF0/ITP_EN SRC2
15 PCLK_ICH6 SRC2# 23
R48 0 +/-5% R0402 CGCLK_SMB 46 +VCCP
12,13,15,16,38 SMB_CLK R50 0 +/-5% R0402 CGDAT_SMB SCLOCK R47 33 +/-5% R0402
12,13,15,16,38 SMB_DATA 47 SDATA SRC1 19 CLK_PCIE_MCH 11
20 R49 33 +/-5% R0402
SRC1# CLK_PCIE_MCHJ 11
CLK_IREF 39 17 R950 33 +/-5% R0402 @GM
IREF SRC0 DREFssCLK 7
18 R951 33 +/-5% R0402 @GM R51
SRC0# DREFssCLKJ 7
1K
13 14 R52 33 +/-5% R0402 @GM +/-1%
VSS_48 DOT96 DREFCLK 7
R54 51 15 R53 33 +/-5% R0402 @GM R0402
VSS_REF DOT96# DREFCLKJ 7
475 45 Dummy
+/-1% VSS_CPU R55 0 Dummy BSEL1
29 VSS_SRC 6 CPU_BSEL1
R0402 6 10 CKGEN_ENJ +/-5% R0402
VSS_PCI1 VTT_PWRGD#/PD CKGEN_ENJ 31
2 R57
VSS_PCI0 R56 12.1 +/-1% R0402 2.2K
REF 52 CLK14_ICH6 15
R58 12.1 +/-1% R0402 R821 1K +/-5%
CLK14_AUDIO 26 7 MCH_BSEL1
CV125 Dummy +/-1% R0402 R0402
B B

+VCCP

R60
1K
+/-1%
R0402
+3V
R61 0 Dummy BSEL0
6 CPU_BSEL0 +/-5% R0402

R62
R63 R822 1K 2.2K
10K 7 MCH_BSEL0 +/-1% R0402 +/-5%
+/-5% R0402
R0402 Dummy

A FSA 100_96_sel A

R64 R952
10K 10K
+/-5% R0402
R0402
+/-5% TECHNOLOGY COPR.
Dummy
Title
Clock Generator
Document Number R ev

S04 MAINBOARD A
Date: Monday, June 14, 2004 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1

hocnghetructuyen.vn
U2A
HAJ[3..31] H DJ[0..63]
7 HAJ[3..31] HAJ3 HD J0 HDJ[0..63] 7
P4 A3# D0# A19
HAJ4 HD J1
HAJ5
HAJ6
U4
V3
A4#
A5#
Dothan D1#
D2#
A25
A22 HD J2
HD J3
R3 A6# D3# B21
HAJ7 V2 A24 HD J4 +3V
A7# D4#
HAJ8
HAJ9
W1
T4
A8# 1 OF 3 D5# B26
A21
HD J5