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5 4 3 2 1
Collected by:
MSI Digitally signed by fdsf
DN: cn=fdsf, o=fsdfsd, DESKTOP ATHLON64 DDR200,266,333,400 UNBUFFERED DDR
DIMM1,3
128bit
939-Pin uFCPGA 939 7
ou=ffsdf,
D
MS-7050-130 email=fdfsd@fsdff, c=US DDR200,266,333,400
184-PIN DDR FIRST LOGICAL DIMM
UNBUFFERED DDR D
Date: 2009.10.09 5,6,9
DIMM2,4
8
07:26:39 +07'00' HyperTransport LINK0
184-PIN DDR SECOND LOGICAL DIMM
LINK0
16x16
ATI NB
External Clock Generator
DESKTOP RS480
HyperTransport LINK0 CPU I/F
ICS951412 16 INTEGRATED GRAPHICS
2X PCI Express Link
VGA CON CRT
17
1 PCI-E SLOTS PCIE 16X
23 PCIE 16X 10,11,12,13,14,15
23
C C
RJ45 Gbit/10/100 1X PCI-E Link OR PCI BUS 1X PCI-E Link 2X PCIE
32 ETHERNET 32
ATI SB
USB-7 USB-6 USB-5 USB-4 USB-3 USB-2 USB-1 USB-0 USB 2.0
DESKTOP SB400 AC LINK AC97 CODEC AC97 JACK
28 28 27 27 27 27 27 27
USB2.0 (4+4) 31 31
SATA
AC97 2.2
SATA Port #1~#2
ATA 66/100 SATA Link
20
ACPI 1.1
PCI BUS
LPC I/F
INT RTC
ATA 66/100 IDE1
PCI/PCI BDGE
29
B
PCI SLOT 1 PCI SLOT 0 18,19,20,21,22 B
25 25
LPC I/F
DESKTOP ATHLON64
Board Stack-up POWER
33
FLASH
1/2 oz. Cu plus SMSC LPC SIO 47M397 TCPA BIOS
plating 24 36 26
Solder
RS480 CORE & PCIE
Mask POWER
34,35
PREPREG 4.5mils
1 oz. Cu Power
Plane
ACPI CONTROLLER & EMCT03 KBD SERIAL FAN
DDR MEMORY HARDWARE FLOPPY LPT
MOUSE PORTS CONTROL
34
POWER MONITOR 24 30 24 30 36
CORE 47mils 24
A A
1 oz. Cu Ground
Plane Micro Star Restricted Secret
PREPREG 4.5mils Title Rev
01.BLOCK DIAGRAM 130
Solder Document Number MS-7050
Mask
1/2 oz. Cu plus MICRO-STAR INT'L CO.,LTD. Last Revision Date:
No. 69, Li-De St, Jung-He City, Tuesday, April 19, 2005
plating Taipei Hsien, Taiwan Sheet
www.kythuatvitinh.com
http://www.msi.com.tw 1 of 41
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TABLE OF CONTENTS
D D
P01: BLOCK DIAGRAM P24: SIO-47M397 & KB/MS
SMBUS ADDRESS
P02: TABLE OF CONTENTS P25: PCI SLOTS 1 & 2
CLOCK GEN. : D2
P03: POWER DELIVERY CHART P26: BIOS ROM
SIO : 5A
P04: CLOCK DISTRIBUTION P27: REAR USB 2.0 PORTS 0,1,2,3,4,5
MS6 : 5E
P05: ATHLON64 HT I/F CTRL & DEBUG P28: FRONT USB 2.0 PORTS 6,7
DIMM : A0,A2
P06: ATHLON64 DDR MEMORY I/F P29: ATA 66/100 EIDE & CD ROM
DVI : 70 (READ)
P07: FIRST LOGICAL DDR DIMM P30: COM PORT & LPT
DVI : 71 (WRITE)
P08: SECOND LOGICAL DDR DIMM P31: AC97 2.3 CODEC
P09: ATHLON64 PWR & GND P32: GIGABIT ETHERNET
C
P10: RS480-HT LINK0 I/F P33: DESKTOP ATHLON64 PWR C
P11: RS480-SIDE PORT MEMORY I/F P34: MS6 ACPI CONTROLLER
P12: RS480-PCIE LINK I/F P35: POWER REGULATOR
P13: RS480-VIDEO I/F & CLKGEN P36: ATX CON. /FAN/FRONT PANEL
P14: RS480-POWER P37: BLEED OFF/LED/HOOD SENCE
P15: RS480-STRAPS P38: DVI CONNECTOR
P16: EXTERNAL CLOCK GENERATOR P39: CHANGE HISTORY
P17: VGA CON. P40: MANUAL PARTS
P18: SB400- PCI-E/PCI/CPU/LPC
P19: SB400 - APCI/GPIO/AC97/USB
B
P20: SB400 - SATA/IDE B
P21: SB400 - PWR & DECOUPLING
P22: SB400 - STRAPS
P23: PCIE CONNECTOR
A A
Micro Star Restricted Secret
Title Rev
02.TABLE OF CONTENTS 130
Document Number MS-7050
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
No. 69, Li-De St, Jung-He City, Tuesday, April 19, 2005
Taipei Hsien, Taiwan Sheet
www.kythuatvitinh.com
http://www.msi.com.tw 2 of 41
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ATHLON 64
CPU
ATX P/S WITH 1A STBY CURRENT PW VRM SW CPU_VCORE (S0, S1) VDDCORE
VBAT 5VSB REGULATOR 0.8-1.55V 60A
5V 3.3V 12V -12V 12V VTT_DDR_SUS (S0,S1,S3)
+/-5% +/-5% +/-5% +/-5% +/-5% DDR400 MEM I/F
+/-5% VCC_DDR(S0,S1,S3) VTT 2A, VDD 2A
VDD 1.2V SW VDDA_1V2 (S0, S1)
VLDT 1.2V 0.5A
REGULATOR NB RS480M
VDDHT
VDDHT 1.2V 0.5A
D D
PCIE_VDD12 PCI-E CORE
&VCO 2.25A
VCC_NB (S0, S1)
NB CORE VDDC
1.0-1.2V 5A
VCC 2.5V AVDD(S0, S1)
LVDS 2.5V 300mA
REGULATOR DAC 200mA
LVDDR18
PLL & DAC-Q 0.1A
1.8V +1.8V_S0 (S0, S1) PCIE_VDD18
1.8V_S3 +1.8V_S3 PCI-E I/O 750mA
REGULATOR VDD18
REGULATOR LVDS 1.8V 100mA
1.25V VTT_DDR VDDQ 1.8V SIDE PORT MEM I/F 2A
REGULATOR DDR400 DIMMs REGULATOR +1.8VDUAL_SPMEM(S0,S1,S3)
VTT_DDR_SUS (S0,S1,S3)
2.5V VDDR
REGULATOR VTT_DDR 2A
VCC_DDR(S0,S1,S3) SB SB400
VDD MEM 12A
X4 PCI-E 0.8A
+3.3VSB (S0, S1, S3, S4, S5)
+3V_Dual (S0, S1, S3) ATA I/O 0.2A
+3.3VSB REGULATOR
ACPI CONTROLLER ATA PLL 0.01A
PCI-E PVDD 80mA
C C
+5VSB REGULATOR +5V_Dual (S0, S1, S3) SB CORE 0.6A
ACPI CONTROLLER 1.8V S5 PW 0.22A
1.8V STB LDO +1.8VSB (S0, S1, S3, S4, S5) 3.3V S5 PW 0.01A
REGULATOR
USB CORE I/O 0.2A
3.3V I/O 0.45A
+1.8V_S3 (S0,S1,S3)
+3.3V (S0, S1) 1.8V USB
RTCVCC
AC97 CODEC
5VAA LDO 3.3V CORE 0.3A
+5VR (S0, S1)
REGULATOR 5V ANALOG 0.1A
ENTHERNET
3.3V 0.5A (S0, S1)
B
3.3V 0.1A (S0,S1,S3) B
SUPER I/O
+3V SD 0.01A
+3V 0.1A
VBAT
PCI Slot (per slot) X1 PCIE per X16 PCIE USB X2 FR USB X6 RL 2XPS/2
5V 5.0A 3.3V 3.0A 3.3V 3.0A VDD VDD 5VDual
3.3V 7.6A 5VDual 5VDual
12V 0.5A 12V 5.5A 1.0A
A
12V 0.5A 1.0A 3.0A A
3.3Vaux 0.1A
3.3Vaux 0.375A
-12V 0.1A
Micro Star Restricted Secret
Title Rev
03.POWER DELIVERY CHART 130
+3.3VDUAL (S0, S1, S3)
Document Number MS-7050
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
No. 69, Li-De St, Jung-He City, Tuesday, April 19, 2005
Taipei Hsien, Taiwan Sheet
www.kythuatvitinh.com
http://www.msi.com.tw 3 of 41
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D D
PCI CLKFB
PCI CLK
DIMM1,3 DIMM2,4
33MHZ
PCI CLK0
PCI SLOT0
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
33MHZ
PCI CLK1
PCI SLOT1
33MHZ
1PAIR NB CLK
66MHZ
C ATI RS480 SB-OSC ATI SB C
ATHLON 64 FX 1 PAIR CPU CLK NB-OSC 14.318MHZ
200MHZ 14.318MHZ
LGA939 PACKAGE 14.318MHZ OSC INPUT SB400
(OPTION) PCI CLK3 ETHERNET 25MHZ OSC INPUT
TVCLKIN
33MHZ PCI Gbit/100/10
NB PCIE CLK
100MHZ
SB PCIE CLK
100MHZ RTC_CLK
32.768KHZ
EXTERNAL PCIE CLK PCI CLK6 KB_CLK
14.318MHZ OSC INPUT SUPER IO KEYBOARD
CLK GEN. 100MHZ PCIE GFX SLOT - 16 LANES 33MHZ
47M397
SIO_CLK MS_CLK
PCIE CLK 14.318MHZ MOUSE
100MHZ PCIE GPP SLOT 0 - 1 LANE
PCIE CLK AC97_BITCLK 14.318MHZ
AC97 CODEC
100MHZ PCIE Gbit Ethernet
B B
14.318MHZ OUTPUT PCIE CLK
100MHZ 32.768KHZ OSC INPUT
14.318MHZ OUTPUT USB CLK
48MHZ 25MHZ OSC INPUT FOR SATA
48MHZ OSC INPUT FOR USB
(OPTION) RTC_CLK
TCPA CONN.
32.768KHZ
A A
Micro Star Restricted Secret
Title Rev
04.CLOCK DISTRIBUTION 130
Document Number MS-7050
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
No. 69, Li-De St, Jung-He City, Tuesday, April 19, 2005
Taipei Hsien, Taiwan Sheet
www.kythuatvitinh.com
http://www.msi.com.tw 4 of 41
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RN2 VCC_DDR
8P4R-680 VDDA_25 VDDA_25 VDDA25 RN1
HT_CADIN_H[15..0] 1 2 80S/0805 8 7 LDT_RST_G
(10) HT_CADIN_H[15..0]
CPU_STRAP_HI_AF12 3 4 2 1 L41 6 5 LDT_PG
HT_CADIN_L[15..0] CPU_STRAP_HI_AJ12 5 6 4 3 LDTSTOP#
(10) HT_CADIN_L[15..0]
VCCA_1V2 VCC1_2HT CPU_STRAP_LO_AH10 7 8 2 1 CPU_THRIP#
HT_CADOUT_H[15..0] 80S/0805 CPU_STRAP_LO_AJ10 1 2
(10) HT_CADOUT_H[15..0]
2 1 L1 CPU_STRAP_LO_AF10 3 4 X_8P4R-680
HT_CADOUT_L[15..0] CPU_STRAP_LO_AH6 5 6
(10) HT_CADOUT_L[15..0]
CPU_STRAP_LO_AG9 7 8
D
VDDA25 D
RN3
8P4R-680
C1 C2 C3
475P/1206 224P 103P CPU1D
C3 AG10 CPU_THRIP#
VDDA3 THERMTRIP_L
B3 VDDA2
VCC1_2HT VCC1_2HT A3 AJ2 SM_THERMDA
VDDA1 THERMDA SM_THERMDA (24)
CPU1A AJ1 SM_THERMDC
THERMDC SM_THERMDC (24)
E2 AG4 LDT_RST_G F8 VID[0..4] (33)
VLDT_06 VLDT_08 VCC1_2HT C641 LDT_PG RESET_L VID4
E1 VLDT_05 VLDT_07 AG3 E8 PWROK VID4 A13
C4 C5 C6 C7 F1 AG1 C8 C9 C10 C11 C12 LDTSTOP# B6 A12 VID3
224P 224P 224P 224P VLDT_02 VLDT_04 475P/1206 224P 224P 224P 224P X_102P LDTSTOP_L VID3 VID2
F2 VLDT_01 VLDT_03 AG2 VID2 C12
R1 44.2RST CPU_L0_REF1 D1 A11 VID1
R2 44.2RST CPU_L0_REF0 L0_REF1 VID1 VID0
C1 L0_REF0 VID0 A10
HT_CADIN_H15 R5 V4 HT_CADOUT_H15
HT_CADIN_L15 L0_CADIN_H15 L0_CADOUT_H15 HT_CADOUT_L15 COREFB+ E5 CPU_NC_C13
T5 L0_CADIN_L15 L0_CADOUT_L15 V3 (33) COREFB+ COREFB_H BP3 C13 TP1
HT_CADIN_H14 P3 Y5 HT_CADOUT_H14 C13 C14 COREFB- E6 E9 CPU_NC_E9
L0_CADIN_H14 L0_CADOUT_H14 (33) COREFB- COREFB_L BP2 TP2
HT_CADIN_L14 P4 W5 HT_CADOUT_L14 C15 E7 B13 CPU_STRAP_LO_B13 R3 680
L0_CADIN_L14 L0_CADOUT_L14 VCC_DDR TP3 CORESENSE BP1
HT_CADIN_H13 N5 Y4 HT_CADOUT_H13 102P 102P CPU_CORESENSE C10 CPU_STRAP_LO_C10 R4 680
L0_CADIN_H13 L0_CADOUT_H13 (16) CPU_CLK TP4 BP0
HT_CADIN_L13 P5 Y3 HT_CADOUT_L13 CPU_VDDIOFB_H Y24
L0_CADIN_L13 L0_CADOUT_L13 TP5 VDDIOFB_H
HT_CADIN_H12 M3 AB5 HT_CADOUT_H12 392p CPU_VDDIOFB_L AA24
L0_CADIN_H12 L0_CADOUT_H12 TP6 VDDIOFB_L
HT_CADIN_L12 M4 AA5 HT_CADOUT_L12 15:5:5:15 R5 AE13
HT_CADIN_H11 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUT_H11 169RST (34