Text preview for : Compal_LA-4092P.pdf part of Compal Compal LA-4092P Compal Compal_LA-4092P.pdf
Back to : Compal_LA-4092P.pdf | Home
A B C D E
1 1
2
Compal confidential 2
JBK00 LA-4092P Schematics Document
Mobile AMD S1G2 CPU with ATI
3
RX781 & SB700 core logic with M82-S 3
2008-02-20
REV:0.4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4092P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 21, 2008 Sheet 1 of 53
A B C D E
A B C D E
Compal Consumer AMD UMA/DISCRETE 17"
confidential
DDR2 667MHz 1.8V
72QFN
1
Thermal Sensor AMD S1G2 CPU DDR2 800MHz 1.8V DDR2-SO-DIMM X2 1
BANK 0, 1, 2, 3 P8, 9 Clock Generator
VRAM ADM1032ARMZ SLG8SP626
638-PIN uFCPGA 638
256MB P6
Dual Channel P22
page 19, 20 P4, 5, 6, 7
Fan conn P4
Hyper Transport Link
16X16
Discrete
ATI M82-S PCI-E Lane*16
P15,16,17,18,21
ATI RX781M Finger Print
P39
LVDS Panel
Interface P24
USB Camera
2
P10, 11, 12, 13, 14 with Digital MIC P39
2
CRT
P23
USB2.0 X12
A-Link Express II USB conn x4
P39
4X PCI-E
HDMI
P25
BT Conn
P39
PCI-E BUS*5 Azalia
ATI SB700 SATA Master-1
SATA Master-2
Touch Screen
SATA Slave P39
RTL8111C Mini-Card*2 Express Card
SATA Slave
WLAN & TV Tunner P33
10/100/1000 P26, 27, 28, 29, 30
Dock
P32 P33 P43
LED
P42
3
RJ45 Conn. LPC BUS Audio CKT AMP & Audio Jack 3
P32 Codec_92HD71B7 TPA6020A2 P37
RTC CKT. P36
P26
MDC V1.5 SUBAMP
SPI ENE P42
TPA3007D1 P38
Power OK CKT. JMB380 SPI ROM KB926 P41
P34 P40
SATA HDD Connector
P31
Int.KBD Subwoofer
P38
CardReader 1394 Conn. Touch Pad CONN.
P41
P34 P34 P42
Docking CKT. CIR SATA ODD Connector
P43 P31
P37
SATA 2nd HDD Option Connector
P31
DC/DC Interface CKT.
P44
4 4
e-SATA Connector
P39
ACCELEROMETER.
LIS302DLTR P35 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4092P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 21, 2008 Sheet 2 of 53
A B C D E
A B C D E
Voltage Rails
Symbol Note :
+5VS
1
+3VS : means Digital Ground 1
power +2.5VS
plane +1.8VS
+1.5VS : means Analog Ground
+1.1VS
+B +1.8V
+5VALW +VGA_CORE @ : means just reserve , no build
+3VL +3VALW +0.9V
+5VL
+1.2VALW
+3V_LAN
+1.2V_HT DEBUG@ : means just reserve for debug.
+CPU_CORE_NB
State
+CPU_CORE_0 Layout Notes
L
+CPU_CORE_1
S0
O O O O
S1
2
O O O O 2
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
O MEANS ON X MEANS OFF
I2C / SMBUS ADDRESSING
SMBUS Control Table
THERMAL
DEVICE HEX ADDRESS SOURCE INVERTER BATT
SERIAL
EEPROM
SENSOR
CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
ADM1032 I / II Slot 2
3
DDR SO-DIMM 0 A0 10100000 3
SMB_EC_CK1
DDR SO-DIMM 1 A4 10100100
SMB_EC_DA1
KB926 X V V X X X X X X X
CLOCK GENERATOR (EXT.) D2 11010010
SMB_EC_CK2
ACCELEROMETER 3A 00111010
SMB_EC_DA2
KB926 X X X V X X X X X X
I2C_CLK
I2C_DATA
RS780M
X X X X X X X V X X
DDC_CLK0
DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
EC SM Bus1 address EC SM Bus2 address RS780M X X X X X X X X X X
DDC_DATA1
Device HEX Address Device HEX Address SCL0
Smart Battery 16H 0001 011X b
ADI1032-2 CPU 9AH 1001 101X b SDA0
SB700 X X X X V V X X X V
ADI1032-1 VGA 98H 1001 100X b SCL1
24C16
CPU SIC interface
A0H
98H
1010 000X b
1001 100X b
SDA1
SB700 X X X X X X V X X X
SCL2
SDA2
SB700 X X X X X X X X X X
4 4
SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4092P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 21, 2008 Sheet 3 of 53
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
Near CPU Socket
+1.2V_HT
JP1A
2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 +VLDT_B 1 2
D2 AE3 C7 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15
H_CADIN15
N5
P5
L0_CADIN_L14
L0_CADIN_H15
L0_CADOUT_L14
L0_CADOUT_H15 T4
T3
H_CADOP15
H_CADON15
PWM Fan Control circuit +5VS
L0_CADIN_L15 L0_CADOUT_L15
10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10
10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
J5 Y4 JP2
10 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 10
1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10 1 1 1 1
C8 C9 2
D1 @ 0.1U_0402_16V4Z 2
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
10 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 10 2 2 GND
10 H_CTLIP1 P3 T5 H_CTLOP1 10 4
2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
ACES_88231-02001
+VCC_FAN
6090022100G_B CONN@
1
2
5
6
1
D Q1 @ D2
G
3 RLZ5.1B_LL34
41 FAN_PWM S SI3456BDV-T1-E3_TSOP6
2
4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4092P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 21, 2008 Sheet 4 of 53
A B C D E
A B C D E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH JP1C
9 DDR_B_D[63..0]
MEM:DATA
DDR_A_D[63..0] 8
DDR_A_CLK0 DDR_B_D0 C11 G12 DDR_A_D0
1 +1.8V DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDR_B_D2 A14 H14 DDR_A_D2
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
2
1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4
R1 DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDR_B_D6 D12 C13 DDR_A_D6
DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 MB_DATA7 MA_DATA7 E13
1 DDR_B_D8 A15 H15 DDR_A_D8
1
+MCH_REF DDR_B_D9 MB_DATA8 MA_DATA8 DDR_A_D9
A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z
C11 DDR_B_D10 A19 E17 DDR_A_D10
MB_DATA10 MA_DATA10
2
1 1 1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11
2 MB_DATA11 MA_DATA11
C12
C13
R2 DDR_A_CLK#1 DDR_B_D12 C14 E14 DDR_A_D12
1K_0402_1% DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13
D14 MB_DATA13 MA_DATA13 F14
DDR_B_D14 C18 C17 DDR_A_D14
2 2 DDR_B_CLK0 DDR_B_D15 MB_DATA14 MA_DATA14 DDR_A_D15
D18 G17
1
DDR_B_D16 MB_DATA15 MA_DATA15 DDR_A_D16
1 D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17