05_WD76C20.pdf part of Western Digital 05 WD76C20 05_WD76C20.pdf, Western Digital _dataBooks 1992_SystemLogic_Imaging_Storage 05

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WD76C20lLV

TABLE OF CONTENTS
Section Title Page

1.0 INTRODUCTION 5-1
1.1 Document Scope 5-1
1.2 Features 5-1
1.3 General Description 5-3

2.0 ARCHITECTURE 5-4
2.1 Bus Interface Logic 5-5
2.2 Chip Select Logic . 5-5
2.3 Floppy Disk Controller 5-5
2.4 Real Time Clock and SRAM 5-5
2.5 Suspend/Resume Logic 5-5
3.0 SIGNAL DESCRIPTION 5-6

4.0 CHIP SELECT LOGIC 5-15

5.0 FLOPPY DISK CONTROLLER 5-18
5.1 765A-Compatible Core 5-18
5.1 .1 Clock and Timing Generator 5-18
5.1.1.1 SCLK 5-18
5.1.1.2 WCLK . . . . 5-19
5.1.1.3 MCLK 5-19
5.1.1.4 Automatic Power Down Mode 5-19
5.2 Drive Interface ..... . 5-19
5.2.1 Data Separator . . . 5-20
5.2.2 Write Precompensation 5-20
5.3 Host Interface . . . . . . . 5-20
5.3.1 Control Register 5-21
5.3.2 Disk Interface Control Register 5-22
5.3.3 Operations Register 5-22
5.3.4 Master Status Registers 5-23
5.3.4.1 MSR1: Power Down and PS/2 Support 5-23
5.3.4.2 MSR: FDC Status Information 5-24
5.3.4.3 Overrun Error Status Reporting 5-25
5.3.5 Status Registers 5-26
5.3.5.1 Status Register 0 5-26
5.3.5.2 Status Register 1 5-26
5.3.5.3 Status Register 2 5-27
5.3.5.4 Status Register 3 5-28
5.3.6 Data Register 5-29

ADVANCED INFORMA nON 11/21/91 5-i
WD76C20lLV

Section Title Page
6.0 IDE DRIVE INTERFACE 5-30
6.1 IDE Drive Signal Logic 5-30
6.2 Chip Select 5-30
6.3 IDE/FDD Drive Selection 5-30
6.4 IDE ReadIWrite 5-30
6.5 IDE Drive Select 5-30
6.6 Data Path Select 5-30

7.0 REAL TIME CLOCK 5-31
7.1 Time Base Oscillator Circuit 5-32
7.2 Power Switch 5-32
7.3 Bus Interface 5-32
7.4 Clock Divider 5-32
7.5 Periodic Interrupt 5-33
7.6 BCD/Binary Increment & Clock/Calendar Update 5-33
7.7 Operational Registers 5-33
7.7.1 Setting Correct Time 5-33
7.7.2 Setting Alarm Intervals 5-34
7.7.3 RTC Register A 5-34
7.7.4 RTC Register B 5-35
7.7.5 RTC Register C 5-36
7.7.6 RTC Register D 5-37

8.0 POWER MANAGEMENT: SUSPEND/RESUME LOGIC 5-38
8.1 Overview 5-38
8.1.1 Suspending the System 5-38
8.1.2 Resuming the System 5-39
8.2 PDREF 5-42
8.3 14 MHZ Crystal Specifications 5-42
8.4 Pin States During Power Down 5-43

9.0 SPECIFICATIONS 5-46
9.1 Maximum Ratings , 5-46
9.2 DC Operating Characteristics 5-46
9.3 Crystal Capacitance 5-47

10.0 AC OPERATING CHARACTERISTICS 5-48
10.1 Floppy Disk Controller Specifications 5-48
10.2 Real Time Clock Specifications 5-56
10.3 IDE Interface Timing 5-62
10.4 Suspend/Resume Timing 5-66

11.0 PACKAGE DIMENSIONS 5-70

A.O WD76C20LV DEVICE SPECIFICATIONS 5-72

5-ii ADVANCED INFORMA TlON 11121191
~
WD76C20lLV

LIST OF TABLES
Table Title Page

3-1 Pin Assignments (Alphabetical Order) 5-7
3-2 Pin Assignments (Numerical Order) 5-7
3-3 Signal Descriptions 5-8
4-1 Chip Select Line Decoder 5-16
4-2 1/0 Address and Chip Select Assignments 5-17
5-1 FDC Sampling (SCLK) Clock 5-18
5-2 FDC MCLK & WCLK Generation 5-19
5-3 FDC Register Map 5-21
5-4 FCLK1 Data Rate Decoder 5-22
5-5 Drive Select Decode 5-23
5-6 MSR/DDR Decode 5-23
5-7 PS/2 Support Sequence 5-24
5-8 Data Register Decode 5-29
6-1 IDE Chip Select Assignments 5-30
7-1 RTC Data Modes 5-34
7-2 RTC Periodic Interrupt Rate Decoder 5-35
8-1 Pin States During Power-Down 5-43
9-1 DC Characteristics 5-46
9-2 Crystal Capacitance 5-47
10-1 FDC Read Timing Specification 5-48
10-2 FDC Read wi Bale Timing Specification 5-49
10-3 FDC Write Timing Specification 5-50
10-4 FDC Write w/Bale Timing Specification 5-51
10-5 FDC DMA Timing Specification 5-52
10-6 FDC Terminal Count Timing Specification 5-53
10-7 FDC 16 MHz Clock Timing Specification 5-54
10-8 FDC Disk Drive Timing Specification 5-55
10-9 RTC and RAM Read Timing Specification 5-56
10-10 RTC and RAM Write w/Bale Timing Specification 5-57
10-11 RTC and Ram Write Timing Specification 5-58
10-12 RTC and RAM Read w/Bale Timing Specification 5-59
10-13 RTCIRQ Release Timing Specification 5-60
10-14 Reset Timing Specification 5-61
10-15 IDE Interface Timing (lDED7 TO DB7) 5-62
10-16 IDE Interface w/Bale Timing (lDED7 TO DB7) 5-63
10-17 IDE Interface Timing (DB7 TO IDED7) 5-64
10-18 IDE Interface w/Bale Timing (DB7 TO IDED7) 5-65
10-19 Resume to Suspend Support Timing 5-66
10-20 Suspend to Resume Support Timing 5-67
10-21 Chip Select Logic Decode Timing 5-68

Ie ADVANCED INFORMATION 11/21/91 5-iii
WD76C20lLV

10-22 Chip Select Logic Decode w/Bale Timing 5-69
A-1 D.C. Characteristics (WD76C20LV) 5-72
A-2 Crystal Capacitance for WD76C20LV . . 5-74

5-iv ADVANCED INFORMA TlON 11/21/91
WD76C20lLV

LIST OF ILLUSTRATIONS
Figure Title Page

1-1 System Level Functional Block Diagram 5-2
2-1 WD76C20 Functional Block Diagram 5-4
3-1 WD76C20 Pin Diagram 5-6
4-1 Chip Select Block Diagram 5-15
5-1 16 MHz Crystal 5-18
7-1 RTC Block Diagram 5-31
7-2 VBAT External Support 5-32
7-3 RTC Crystal External Circuitry 5-32
7-4 RTC Crystal Parameters 5-32
7-5 RTC Address Map 5-33
8-1 Suspend/Resume/Sleep Mode Cycle 5-40
8-2 Full Power Down-Mode System Block Diagram 5-41
8-3 14 MHz Clock Generation 5-42
10-1 FDC Read Timing Diagram 5-48
10-2 FDC Read w/Bale Timing Diagram 5-49
10-3 FDC Write Timing Diagram 5-50
10-4 FDC Write w/Bale Timing Diagram 5-51
10-5 FDC DMA Timing Diagram 5-52
10-6 FDC Terminal Count Timing Diagram 5-53
10-7 FDC 16 MHz Clock Timing Diagram 5-54
10-8 FDC Disk Drive Timing Diagram 5-55
10-9 RTC and RAM Read Timing Diagram 5-56
10-10 RTC and RAM Read w/Bale Timing Diagram 5-57
10-11 RTC and RAM Write Timing Diagram 5-58
10-12 RTC and RAM Read w/Bale Timing Diagram 5-59
10-13 RTC IRQ Release Timing Diagram 5-60
10-14 Reset Timing Diagram 5-61
10-15 IDE Interface Timing Diagram (lDED7 TO DB7) 5-62
10-16 IDE Interface w/Bale Timing (lDED7 TO DB7) 5-63
10-17 IDE Interface Timing (DB7 TO IDED7) 5-64
10-18 IDE Interface w/Bale Timing (DB7 TO IDED7) 5-65
10-19 Resume To Suspend Support Timing 5-66
10-20 Suspend To Resume Support Timing 5-67
10-21 Chip Select Logic Decode Timing 5-68
10-22 Chip Select Logic w/Bale Timing 5-69
11-1 WD76C20 Package Diagram (84-Pin PLCC) 5-70
11-2 WD76C20 Package Diagram (84-Pin PQFP) 5-71
A-1 VBAT External Support 5-73
A-2 RTC Crystal External Circuitry 5-73
A-3 RTC Crystal Parameters 5-73

~ ADVANCED INFORMATION 11/21/91 5-v
INTRODUCTION WD76C20lLV

1.0 INTRODUCTION
1.1 DOCUMENT SCOPE On chip clock generation:
This data sheet applies to both the WD76C20, and
2 TTL clock inputs, or
WD76C20LV. The WD90C20LV is a low voltage
version of the W076C20 chip. For convenience all Single 16 or 32 MHz crystal circuit
references to these two devices will be referred to and one TTL clock input
as the WD76C20.
Power Qualified Reset
See Appendix A for the specification differences of
the WD76C20LV. Enable PQR in W076C20
Disable PQR in W076C20LV

1.2 FEATURES Host interface read/write accesses com-
patible with 80286 microprocessors at
The WD76C20 includes these features: speeds up to 12 MHz with 0 wait states