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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER
LAYER
1
2
: TOP
:GND
LX89 SYSTEM DIAGRAM 01
DDR3-SODIMM1 DDR3 channel A
LAYER 3 : IN1
AMD Champlain CPU THERMAL
LAYER 4 : IN2 PAGE 6,7
35mm X 35mm
SENSOR 14.318MHz
LAYER 5 : VCC
A A
LAYER 6 : BOT S1G4 Processor PAGE 5
DDR3-SODIMM2 DDR3 channel B
638P (PGA)45W/35W
PAGE 6,7 PAGE 3,4,5 CPU_CLK CLOCK GEN
NBGFX_CLK ICS9LPRS476AKLFT-->HP
NBGPP_CLK SLG8SP628VTR-->HP
SBLINK_CLK RTM880N-796 -->HP
HT3 PAGE 2
PCI-Express 16X ATI
PCI-E HDMI HDMI
Side port
PARK-PRO 64 bit PAGE 27
Madison 128 bit
X1 X1 NORTH BRIDGE 29mm X 29mm
CRT
CRT
Mini PCI-E DDR3 RAM PAGE 17,18,19 MUXs PAGE 25
LAN RS880
Realtek Card UMA Only 20,21 (S.G)
PAGE 8 LVDS PAGE 26
PCIE-LAN
RTL8111D
A12 LVDS
(Wireless LAN) DDR3 800MHz
B
(10/100/1000)
21mm X 21mm, 528pin BGA PAGE 24 B
VRAM
PAGE 32 PAGE 35 CRT
64MX16X4,64 bit
PAGE 8,9,10,11 LVDS
64MX16X8,128 bit
PAGE 22,23
RJ45
ALINK X4
PAGE 32
SYSTEM CHARGER(ISL6251)
PAGE 40 SATA0 150MB
SATA - HDD1 BT softbreeze FP
SOUTH BRIDGE PAGE 34 Touch
SYSTEM POWER ISL6237
PAGE 34 VFM301
PAGE 34 Screen
PAGE 34 SATA1 150MB 15 PAGE 24
SATA - CD-ROM SB820
14
PAGE 34 21mm X 21mm, 528pin BGA USB1.1
DDR II SMDDR_VTERM
1.8V/1.8VSUS(RT8207) 4.5W(Ext)
PAGE 37 SATA - HDD2
SATA2 150MB 4.3W(Int)
C USB2.0 C
PAGE 34 1,8,9 5 2 3
PAGE 12,13.14.15.16
VCCP +1.1V AND +1.2V(RT8204)
SATA3 150MB USB2.0 Ports Webcam Flash Media
E-SATA RTS5159
PAGE 35 X3 PAGE 29 E-SATA&USB X1 PAGE 23 PCI-E WLAN Card x1
PAGE 33 Combo PAGE 33
Azalia PAGE 26
VGACORE(1.1V~1.2V)Oz8118 I2C LPC
PAGE 38 Accelerometer
STM HP302DL
ENE KBC IDT AUDIO
PAGE 30 92HD80 Amplifier Sub
CPU CORE ISL6265HRTZ-T Woofer
KB3926 Dx PAGE 31 PAGE 31
PAGE 36 PAGE 27
PAGE 37
SMBUS TABLE
Clock gen/Robson/TV tuner Keyboard PAGE 36
SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3V
D Touch Pad PAGE 36 D
epress card Digital MIC AUDIO CONN
FAN SPI Speaker
Wlan Card +3VS5 (Phone/ MIC)
PAGE 28 PAGE 37 PAGE 29 PAGE 30 PAGE 29
PROJECT : LX89
EC --SCL/SD Battery charge/discharge +3VPCU Quanta Computer Inc.
EC--SCL2/SD2 VGA thermal/system thermal +3V Size Document Number Rev
Custom 1A
Block Diagram
NB5/RD2
Date: Monday, September 28, 2009 Sheet 1 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.1V L36
600 ohm, 0.5A
BLM18PG181SN1D(180,1.5A)_6
C417
22U/6.3V_8
C421
0.1U/10V_4
C434
0.1U/10V_4
C422
+1.1V_CLKVDDIO
C420
0.1U/10V_4 0.1U/10V_4
C445
0.1U/10V_4
C426
0.1U/10V_4
02
D 600 ohm, 0.5A +3V_CLKVDD D
L49 +3V_CLKVDD
+3V
BLM18PG181SN1D(180,1.5A)_6
C467
C474 C469 C429 C419 C440 C442 C451 C468 C446
22U/6.3V_8 2.2U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
R242 *261_4 Place within 0.5"
U12
of CLKGEN
+3V_CLKVDD 4 50 CPUCLKP_EXT R253 EXT *0_4 CPUCLKP
VDDDOT CPUK8_0T CPUCLKP 3,12
16 49 CPUCLKN_EXT R252 EXT *0_4 CPUCLKN
VDDSRC CPUK8_0C CPUCLKN 3,12
26 VDDATIG
Place very 35 VDDSB
40 30 NBGFX_CLKP_EXT to NB for external Graphics
close to 48
VDD_SATA ATIG0T
29 NBGFX_CLKN_EXT
NBGFX_CLKP_EXT 10
C/G 55
VDDCPU ATIG0C
28 EXT_GFX_CLKP_EXT R207 EXT *0_4 EXT_GFX_CLKP
NBGFX_CLKN_EXT 10 reference clock
+3V_CLKVDD VDDHTT ATIG1T EXT_GFX_CLKP 12,17
56 27 EXT_GFX_CLKN_EXT R206 EXT *0_4 EXT_GFX_CLKN to PARK -RS880 only
VDDREF ATIG1C EXT_GFX_CLKN 12,17
L46 +3V_CLK_VDDA 63 Clock for Dis only
BLM18PG181SN1D(180,1.5A)_6 VDD48
C470 37 SBLINK_CLKP_EXT R219 EXT *0_4 SBLINK_CLKP
SB_SRC0T SBLINK_CLKP 10,12
C465 11 36 SBLINK_CLKN_EXT R217 EXT *0_4 SBLINK_CLKN to NB for AC-LINK reference clock
VDDSRC_IO SB_SRC0C SBLINK_CLKN 10,12
2.2U/6.3V_6 0.1U/10V_4 17 32 SBSRC_CLKP
C VDDSRC_IO SB_SRC1T SBSRC_CLKP 12 C
25 31 SBSRC_CLKN to SB
VDDATIG_IO SB_SRC1C SBSRC_CLKN 12
34 VDDSB_IO
+1.1V_CLKVDDIO 47 VDDCPU_IO PCIE_MINI1_CLKP_EXT PCIE_MINI1_CLKP
SRC0T 22 R201 EXT *0_4
PCIE_MINI1_CLKP 12,34
21 PCIE_MINI1_CLKN_EXT R202 EXT *0_4 PCIE_MINI1_CLKN to WLAN
SRC0C PCIE_MINI1_CLKN 12,34
1 GND48 SRC1T 20
C482 33P/50V_4 CG_XIN 7 19
GNDDOT SRC1C
10 GNDSRC SRC2T 15
2
18 GNDSRC SRC2C 14
Y2 PCIE_LAN_CLKP_EXT R205 EXT *0_4 PCIE_LAN_CLKP
14.318MHZ
24
33
GNDATIG QFN64 SRC3T 13
12 PCIE_LAN_CLKN_EXT R204 EXT *0_4 PCIE_LAN_CLKN
PCIE_LAN_CLKP 12,32
to LAN
GNDSB SRC3C PCIE_LAN_CLKN 12,32
43 9
1
C483 33P/50V_4 CG_XOUT GNDSATA SRC4T
46 GNDCPU SRC4C 8
52 6 CLK_VGA_27M_SS R226 EXT *33_4
GNDHTT SRC7T/27M_SS T38
60 5 CLK_VGA_27M_NSS R235 EXT *75/F_4
GNDREF SRC7C/27M T41
SRC6T/SATAT 42 R230 EXT *100/F_4
SRC6C/SATAC 41 27Mhz for Dis only
CG_XIN 61
CG_XOUT X1
62 X2
54 NBHTREFCLK0P_EXT R247 EXT *0_4 NBHT_REFCLKP
HTT0T/66M NBHT_REFCLKP 10,12
53 NBHTREFCLK0N_EXT R246 EXT *0_4 NBHT_REFCLKN
HTT0C/66M NBHT_REFCLKN 10,12
PCLK_SMB 2
6,7,13,30,34 PCLK_SMB PDAT_SMB SMBCLK
6,7,13,30,34 PDAT_SMB 3 SMBDAT
64 CLK48MUSB R239 EXT *22_4 CLK_48M_USB
48MHz_0 CLK_48M_USB 13
CLK_PD# 51 PD# SEL_HT66 R250 158/F_4
REF0/SEL_HTT66 59
58 SEL_SATA R268 *33_4
REF1/SEL_SATA EXT_SB_OSC 13
CLKREQ0# 23 57 SEL_27 EXT R258 90.9/F_4
*CLKREQ0# REF2/SEL_27 T46 EXT_NB_OSC 10
CLKREQ4# 38
B CLKREQ3# *CLKREQ4# B
39 *CLKREQ3#
CLKREQ2# 44
CLKREQ1# *CLKREQ2#
For EMI 45 *CLKREQ1#
+3V
TGND
R237 *8.2K_4 CLKREQ1#
C489 *10P/50V_4 EXT_NB_OSC RTM880N-796_QFN64
65
R243 8.2K_4 CLK_PD#
C455 *10P/50V_4 CLK_48M_USB
+3V
R194 *8.2K_4 CLKREQ0#
R233 *8.2K_4 CLKREQ2# +3V_CLKVDD
R224 *8.2K_4 CLKREQ3#
R222 *8.2K_4 CLKREQ4#
if use clock SLG SLG8SP628VTR--AL8SP628000
request pin , need
to pull Hi for
RTL RTM880N-796-- AL000880001
default setting * default R269 R248 Clock chip has internal serial
*8.2K_4 8.2K_4
66 MHz 3.3V single ended HTT clock terminations
1 SEL_27 for differencial pairs, external resistors
SEL_HTT66 SEL_SATA
0* 100 MHz differential HTT clock SEL_HT66
are
reserved for debug purpose.
A 100 MHz non-spreading differential SRC clock not need to A
SEL_SATA 1 R249
R264
stuff ,
8.2K_4
0* 100 MHz spreading differential SRC clock *8.2K_4 R185 have
pull LOW
SEL_27 1* 27MHz non-spreading singled clock
0 100 MHz spreading differential SRC clock RS780M/RX780M
PROJECT : LX89
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Clock Generator
NB5/RD2
Date: Monday, September 28, 2009 Sheet 2 of 46
5 4 3 2 1
5 4 3 2 1
03
BLM21PG221SN1D(220,100M,2A)_8 W/S= 15 mil/20mil CPU_THERMDC
40 +2.5V +CPUVDDA CPU_THERMDA CPU_THERMDC 5
2,8,9,10,11,15,38 +1.1V +2.5V CPU_THERMDA 5
L33 CPU CLK
4,5,6,7,14,39,40,41,42 +1.5VSUS
CPU_PWRGD 300_4 R449
8,11,34,42 +1.5V
C360 LS0805-100M-N C341 C326 C330 CPUCLKP CPU_LDT_RST# 300_4 R136
25,26,27,28,29,30,31,32,33,34,35,36,42 +3V 2,12 CPUCLKP
4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 3300P/50V_4 CPUCLKN CPU_LDT_STOP# 300_4 R121
2,12 CPUCLKN
CPU_LDT_REQ#_CPU *300/F_4 R131 +1.5V
Change +1.1V_VLDT to +1.1V_VLDT_R Keep trace from resisor to CPU within 0.6"
for layout concern +CPUVDDA 250mA
VLDT use 1.5A Max current keep trace from caps to CPU within 1.2" U26D
U26A SI
+1.1V +1.1V_VLDT W/S= 15 mil/20mil
+CPUVDDA F8 M11
R139 *0_6/S C334 10U/6.3V_8 +1.1V_VLDT +1.1V_VLDT_R 10U/6.3V_8 C61 CPUCLKIN R437 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 VSS
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 RSVD11 W 18
C319 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT_R 0.22U/6.3V_4 C51
D C313 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT_R 180P/50V_4 C49 CPUCLKP C715 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
+1.1V SI C310 180P/50V_4 +1.1V_VLDT D4 AE5 +1.1V_VLDT_R CPUCLKN C716 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
+1.1V_VLDT_R VLDT_A3 VLDT_B3 CLKIN_L SVD
R41 *0_6/S HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
HT_NB_CPU_CAD_H1 L0_CADIN_L0 L0_CADOUT_L0 HT_CPU_NB_CAD_H1 12 CPU_PWRGD CPU_LDT_STOP# PW ROK CPU_THERMTRIP_L#
Change +1.1V_VLDT to +1.1V_VLDT_R E1 AC2 10,12 CPU_LDT_STOP# F10 AF6
HT_NB_CPU_CAD_L1 L0_CADIN_H1 L0_CADOUT_H1 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU LDTSTOP_L THERMTRIP_L CPU_PROCHOT_L#
for layout concern F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 C6 LDTREQ_L PROCHOT_L AC7
HT_NB_CPU_CAD_H2 G3 AB1 HT_CPU_NB_CAD_H2 AA8
L0_CADIN_H2 L0_CADOUT_H2 MEMHOT_L T1
HT_NB_CPU_CAD_L2 G2 AA1 HT_CPU_NB_CAD_L2 CPU_SIC AF4
L0_CADIN_L2 L0_CADOUT_L2 5 CPU_SIC SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C 5 CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3