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WD771 OIWD771 OLP

TABLE OF CONTENTS
Section Title Page

1.0 INTRODUCTION 7-1
1.1 Document Scope 7-1
1.2 Features 7-1
1.3 General Description 7-2
1.3.1 WD7710 7-2
1.3.2 WD7710lP 7-2

2.0 ARCHITECTURE 7-4
2.1 Initialization And Clocking 7-4
2.2 AT Bus . . . . . . . 7-4
2.3 Main Processor Control 7-4
2.4 Numeric Processor Control 7-4
2.5 Data Bus . . . . . . . 7-4
2.6 Memory and EMS. Control 7-4
2.7 Power Management Control 7-5
2.8 Register File . . . . . . 7-5
2.8.1 lock Status Register 7-5
2.8.2 lock/Unlock Register 7-6
2.9 VlBI Control . 7-6
2.1 0 Cache Control 7-6

3.0 SIGNAL DESCRIPTION 7-10

4.0 INITIALIZATION AND CLOCKING 7-19
4.1 Power-up Reset 7-19
4.2 Clocking ...... . 7-19
4.2.1 Internal Clock (ClK14) 7-19
4.2.2 System Bus Clock (SYSClK) 7-19
4.2.3 Processor Clock (CPUClK) . 7-19
4.2.4 CPU Clock (CPUClK) Control Register 7-21

5.0 AT BUS 7-24
5.1 Interrupt Multiplexing ........ 7 -24
5.1.1 Data Acknowledge DACK7-5, 3-0 7-24
5.1.2 Data Request DRQIN 7 -24
5.1.3 Interrupt Requests . . . . . . 7-24
5.1.4 AT Address Bus, Data Bus, And Terminal Count (TC) Signal 7-24
5.2 Power Management Control PMCIN ............. 7-24
5.3 Numeric Processor . . . . . . . . . . . . . . . . . . . . 7-26
5.3.1 Numeric Processor Busy, Bus Timing, And Power Down Register 7-26
5.3.2 Numeric Processor Busy (NPBUSY) Reset 7-28
5.3.3 Numeric Processor Reset (NPRST) . . 7-28

e2:e ADVANCED INFORMATION 1112S191 7-i
WD771OIWD 771 OLP

Section Title Page
5.4 DMA Control . . . . . 7-29
5.4.1 Transfer Modes 7-29
5.4.2 Transfer Types 7-29
5.4.3 Autoinitialize 7-30
5.4.4 Priority 7-30
5.4.5 Extended Write 7-30
5.4.6 Base and Current Address 7-30
5.4.7 Base and Current Word Count 7-30
5.4.8 Command Register 7-32
5.4.9 Status Register 7-32
5.4.10 Request Register 7-32
5.4.11 Mask Registers 7-32
5.4.11.1 Single Mask Register 7-33
5.4.11.2 Clear Mask Register 7-33
5.4.11.3 Mask Multiple Register 7-33
5.4.12 Mode Register 7-33
5.4.13 Clear Pointer Register 7-34
5.4.14 Master Clear Register 7-34
5.4.15 DMA Mode Shadow Register 7-35
5.5 System Controller 8259 Interrupt Controllers 7-35
5.5.1 Interrupt Sequence ..... . 7-35
5.5.2 Setup - Initialization Command Words (ICW) 7-37
5.5.2.1 ICW1 - Initialization Command Word 1 7-37
5.5.2.2 ICW2 - Initialization Command Word 2 7-37
5.5.2.3 ICW3 - Initialization Command Word 3 7-37
5.5.2.4 ICW4 -Initialization Command Word 4 7-38
5.5.3 Operation .............. . 7-38
5.5.3.1 OCW1 - Operation Control Word 1 7-38
5.5.3.2 OCW2 - Operation Control Word 2 7-39
5.5.3.3 OCW3 - Operation Control Word 3 7-39
5.6 System Controller 8254 Timer . . . . . . . . . . 7-40
5.6.1 Setup .............. . 7-41
5.6.1.1 Mode 0 Interrupt On Terminal Count 7-41
5.6.1.2 Mode 1 Hardware Retriggerable One Shot 7-41
5.6.1.3 Mode 2 Rate Generator 7-41
5.6.1.4 Mode 3 Square Wave Generator 7-41
5.6.1.5 Mode 4 Software Triggered Strobe 7-41
5.6.1.6 Mode 5 Hardware Triggered Strobe 7-41
5.6.2 Reading The Counter 7-42

7-ii ADVANCED INFORMA TlON 11/25/91
WD7710/WD7710LP

Section Title Page
5.6.3 Reading Status 7-42
5.6.4 Page 7-42
5.6.5 Refresh Address 7-42
5.7 System Controller Decode 7-43
5.7.1 Page Register Decodes 7-43
5.8 NMI and Real-time Clock 7-44
5.8.1 Real-Time Clock. Address Register 7-44
5.8.2 Real-Time Clock Data Register 7-44
5.8.3 Lock Pass, Alternate A20G, And Hot Reset Register 7-44
5.9 Parity Error and I/O Channel Check 7-45

6.0 MEMORY AND EMS CONTROL 7-46
6.1 DRAM Address And Data Bus 7-46
6.2 Memory Configuration . . . 7-47
6.2.1 Memory Control . . 7-47
6.2.2 Memory Bank 3 Through Bank 0 Starting Address 7-49
6.2.3 Split Starting Address ..... . 7-50
6.2.4 RAM Shadow And Write Protect 7-52
6.2.5 High Memory Write Protect Boundary 7-54
6.3 Memory Timing ........... . 7-55
6.3.1 Non-page Mode DRAM Memory Timing 7-55
6.3.2 Page Mode ..... . 7-58
6.3.3 Memory Address Multiplexer . . . . . 7-59
6.4 EMS . . . . . . . . . . . . . . . . . . 7-61
6.4.1 EMS Control And Lower EMS Boundary 7-61
6.4.2 EMS Page Register Pointer 7-62
6.4.3 EMS Page Register 7-64

7.0 CACHE CONTROLLER . . . . . 7-65
7.1 Cache Architecture 7-65
7.1.1 Processor Interface 7-65
7.1.2 Tag RAM 7-65
7.1.3 Data RAM 7-66
7.1.4 Snoop Interface 7-66
7.1.5 Noncacheable Control 7-67
7.1.6 Diagnostic Control Logic 7-67
7.1.7 LRU 7-67
7.1.8 Flush 7-67
7.2 Cache Control Register 7-67
7.2.1 Cacheable Region 1 Upper Boundary 7-68
7.2.2 Noncacheable Region 1 Lower Boundary 7-69
7.2.3 Noncacheable Region 2 Lower Boundary 7-70
7.2.4 Flush . . . . . . . . . . . . . . 7-70

W-
;q. ADVANCED INFORMATION 11/25/91 7-iii
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Section Title Page

8.0 PORT CHIP SELECT AND WD7710LP REFRESH CONTROL 7-71
8.1 Refresh Control, Serial And Parallel Chip Selects 7-71
8.2 RTC, PVGA, 80287 Timing, Disk Chip Selects 7-73
8.3 Programmable Chip Select Address ..... 7-75
8.4 I/O Port Addresses And Chip Select Assignments 7-76

9.0 POWER MANAGEMENT CONTROL 7-78
9.1 System Activity Monitor (SAM) 7-78
9.2 Processor Power Down Mode 7-79
9.3 PMC Output Control Registers 7-82
9.4 PMC Timers . . . . 7-83
9.5 PMC Inputs 7-83
9.6 PMC Interrupt Enables 7-84
9.7 NMI Status 7-85
9.8 Serial/Parallel Shadow Register 7-86
9.9 Interrupt Controller Shadow Register 7-86
9.10 Port 70 Shadow Register . . . 7-87
9.11 Activity Monitor Control Register 7-88
9.12 Activity Monitor Mask Register . 7-90
9.13 3V Suspend Shadow Register . 7-92
9.13.1 DMA Shadow Register 1 7-92
9.13.2 DMA Shadow Register 2 7-93
9.13.3 DMA Shadow Register 3 7-93
9.13.4 DMA Base Address and Count Register 7-94
9.13.5 Timer Count 7-94
9.14 Save And Resume 7-95

10.0 DIAGNOSTIC MODE 7-96
10.1 Diagnostic Register 7-96
10.2 Delay Line Diagnostic Register 7-98
10.3 Test Enable Register 7-98
10.4 Test Status Register . . . . 7-99

11.0 DC ELECTRICAL SPECIFICATIONS .7-101
11.1 Maximum Ratings . . . . . . 7-101
11.2 DC Operating Characteristics . 7-101

12.0 AC OPERATING CHARACTERISTICS .7-104
12.1 Memory Timing . . . . . . . .7-105
12.1.1 80286 Page Mode Timing .7-105
12.1 .2 80286 Non-Page Mode 00 Timing .7-125
12.1.3 80286 Non-Page Mode 01 Timing .7-129
12.1.4 80386SX Page Mode Timing . . .7-132
12.1.5 80386SX Non-Page Mode 00 And Mode 01 Timing .7-137

7-iv ADVANCED INFORMATION 11125/91
WD771 O/WD771 OLP

Section Title Page
12.2 AT Bus Timing ........ . .7-129
12.2.1 CPU Initiated AT Bus Cycles