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8 7 6 5 4 3 2 1
Version 0A
MS-6786 03/24/2003 Update
Cover Sheet 1
VIA (R) KM400(8378) / VT8235CE Chipset
AMD PGA 462 Processor Schematics Block Diagram 2
D
*AMD PGA 462 Processor CLOCK GEN 3
D
*VIA KM400 / VT8235CE Chipset AMD CPU Sockets 462 4-5
(DDR 400 / AGP 8X / VLink 8X) Via KM400 North Bridge 6-8
*Winbond 83697HF-VF LPC I/O DDR SLOT 9
*VT6103 PHY 10 / 100 DDR TERMINATOR 10
*AC'97 Codec ALC650 Codec AGP SLOT 11
*USB 2.0 support (integrated into VT8235) Via VT8237 South Bridge 12 - 14
*AGP SLOT * 1 ( 8X ) PCI SLOTS 15
C
*PCI SLOT * 3 VIA VT6103 LAN PHY 16 C
*CNR SLOT * 1 IDE CONNECTOR 17
*DDR DIMM * 2 USB CONNECTOR 18
AC'97 CODEC 19
MS-6786 Ver:0A
HARDWARE MONITOR 20
Option L BOM (with LAN) LPC I/O(W83697HF) 21
KM400 SMT5010 781 CNR & Fan Control 22
8235CE SMT5020 44 KB/MS & Rear I/O 23
DIP 74
VRM 9.X 24
B
Total 899 B
ACPI Controller, Regulators 25
Front Panel & VGA Connector ATX Connector 26
Decoupling Capacitor 27
Orcad Config ERP BOM Function Description
Create
A Date. A
MS-6786P1 0A With LAN.
6786-A10 BOM 601-6786-A10 MSI Standard MSI Standard KM400+VT8235CE
With LAN. MICRO-STAR INT'L CO.,LTD.
BOM MSI Standard KM400+VT8237CD
Title
COVER PAGE
Size Document Number Rev
MS-6786 0A
Date: Wednesday, March 26, 2003 Sheet 1 of 29
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System Block Diagram + 12V
D - 12V D
Host CLK
PCI CLK + 5V
SOCKET-462 Clock Gen. ATX Conn.
AGP CLK - 5V
3.3V
Host Bus
VCC5SBY
Mem. CLK
SSTL-2 Termination
DDR SDRAM (Only for DDR)
VCC5SBY
AGP Connector VCC3SBY VCCM
AGP CONNECTOR VIA KM400 DIMM 1 DIMM 2 Rtt
VCC3
C VCC25SBY C
V-Link
Analog In
DDR_VTT
AC'97
Audio Codec
PCI SLOT 3 PCI SLOT 2 PCI SLOT 1
VCC2_5
Analog Out
VIA 8237
CNR
IDE 1 IDE 2
KEYBOARD PS/2 VDDQ
/MOUSE
USB 0 USB 3
B Lan Phy VCCA_PLL B
USB 1 USB 4
LPC Bus
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2 VCC5SBY
5VDUAL KBUVCC
TEMPERATURE MONITOR VCC5
LPC Super I/O
Legacy FAN CONTROL
ROM
VCORE
GPIOs IR/CIR SERIAL PARALLEL FLOPPY
A A
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
CustomMS-6786 0A
Date: Wednesday, March 26, 2003 Sheet 2 of 29
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By-Pass Capacitors
Place near to the Clock Outputs
Main Clock Generator Damping Resistors
Place near to the
Clock Outputs
U13
VCC3 ICS950910 VCLKNB C211 10P
CP10
D 5 VDDAGP CPUCLK_PPT 48 7 8 HCLK
HCLK {6}
VCLKSB C219 10P D
16 49 5 6 RN75 HCLK#
VDDPCI CPUCLK_PPC CPUCLK# HCLK# {6} AGPCLK1
X_COPPER 22 3 4 8P4R-10 C212 10P
VDD48M CPUCLK CPUCLK# {4}
51 VDDCPU CPUCLKST 53 1 2 CPUCLK {4}
CB81 CB88 CB87 CB86 CB82 55 52 CN16 8P4C-10P
VDDREF CPUCLKSC PCICLK3 1 2
CE2 3 4
105P 105P 105P 105P 104P 2 44 1 2 PCICLK2 5 6
475P/0805 GND2 DDRT0 DDRCLK0 {9}
9 43 3 4 RN72 PCICLK1 7 8
GND9 DDRC0 DDRCLK-0 {9}
13 42 5 6 8P4R-10
GND13 DDRT1 DDRCLK1 {9}
19 GND48M DDRC1 41 7 8 DDRCLK-1 {9}
33 38 1 2 PCLKSB C214 10P
GND33 DDRT2 DDRCLK2 {9}
39 37 3 4 RN73
GND39 DDRC2 DDRCLK-2 {9}
47 36 5 6 8P4R-10 SIOPCLK C213 10P
GNDI DDRT3 DDRCLK3 {9}
54 GND54 DDRC3 35 7 8 DDRCLK-3 {9}
VCC3 32 1 2
DDRT4 DDRCLK4 {9}
CP11 31 3 4 RN74 APICCPU C182 10P
DDRC4 DDRCLK-4 {9}
23 30 5 6 8P4R-10
AVDD DDRT5 DDRCLK5 {9}
29 7 8 APICSB C210 10P
DDRC5 DDRCLK-5 {9}
X_COPPER 24
CB83 AGND
BUFFER_IN 45 DCLKO {7}
104P 50 46 R188 22 SBCLK14 C208 10P
VCC2_5 VDDI FBOUT DCLKI {7}
VCC2_5
CP9 6 MODE R245 22 USBCLK C215 10P
VADDR25 AGP0/MODE SELCPU VCLKNB {8}
34 7 R268 22
VDD3.3/2.5-34 AGP1/SEL_CPU VCLKSB {14}
CB75 8 R247 22 SIO48M C216 10P
AGP2/PCI_STOP# AGPCLK1 {11}
X_COPPER 40
C164 VDD3.3/2.5-40 DCLKI C115 X_10P
C 105P
105P
PCICLK_F/FS1 10 FS1 1 2 PCICLK3 {15}
C
11 SELDDR# 3 4 RN85
PCICLK0/SEL_SD_DDR# PCICLK1 {15}
12 MULTSEL0 5 6 8P4R-22
PCICLK1/MULTSEL0 PCICLK2 {15} By-Pass Capacitors
PCICLK2 14 7 8
15 Place near to the Clock Buffer
PCICLK3 R251
{9,13,22,25} SMBCLK 27 17 22 PCLKSB {14}
SCLK PCICLK4 R252 CN13 X_8P4C-10P50N
{9,13,22,25} SMBDAT 28 18 22 SIOPCLK {21}
SDATA PCICLK5/CPU_STP# DDRCLK0 1 2
DDRCLK-0 3 4
R222 X_0 26 20 FS3 R253 22 DDRCLK1 5 6
{22,25,26} FP_RST# RESET/PD# 48M/FS3 FS2 USBCLK {12} DDRCLK-1
21 R269 22 7 8
24_48M/FS2 SIO48M {21}
R244 22
VCC3 FS0 APICSB {14}
25 1 R258 33 CN14 X_8P4C-10P50N
IREF REF0/FS0 SBCLK14 {13} DDRCLK2 1 2
R215 56 REF1 R190 62RST DDRCLK-2 3 4
FS3 VTT_PWRGD#/REF1 APICCPU {4}
4.7K R249 DDRCLK3 5 6
XOUT
FS2 4.7K R254 475RST R191 198RST DDRCLK-3 7 8
XIN
R124 22 CN12 X_8P4C-10P50N
GCLK14 {8}
DDRCLK4
3
4
1 2
FS1_S R270 10K FS1 2.7K R255 DDRCLK-4 3 4
Y2 DDRCLK5 5 6
DDRCLK-5 7 8
FS0_S R271 10K FS0 2.7K R256
YCRY14.31818H16P
MULTSEL0 R232 4.7K
C202 C188 HCLK C386 10P
22P 22P SELCPU R246 4.7K HCLK# C387 10P
B CPUCLK# C388 10P B
SELDDR# R248 4.7K CPUCLK C389 10P
Notice: When populate VT8235CE ,RX1&RX2 location will be (1-2).
When populate VT8237CD ,RX1&RX2 location will be (2-3).
VCC2_5
SDA2 VCC3 DCLKO R187 X_4.7K
{13,17} SDA2
1
RX2
SW1
FS1_S 1 YJ103
2 2
3
820 SW1 SW2
PDA2 {3}
PDA2
3
FS1 FS0
100MHz 0 0
133MHz 0 1
166MHz 1 1
SDA0 VCC3
{13,17} SDA0 200MHz 1 0
1
SW2
RX1 YJ103
A 2 FS0_S 1
2
A
3
MICRO-STAR INT'L CO.,LTD.
{3} PDA0 820
PDA0
3
Title
CLOCK GEN
Size Document Number Rev
CustomMS-6786 0A
Date: Wednesday, March 26, 2003 Sheet 3 of 29
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VCORE VCC3
R9 R13
CPU1A X_680 510
SDATA#0 AA35 AE1
{6} SDATA#[0:63] SDATA#1 SDATA0 A20M FERR A20M# {14} VCORE
W37 SDATA1 FERR AG1 FERR# {14}
SDATA#2 W35 AJ3
D
SDATA#3 SDATA2 INIT CPUINIT# {14}
Y35 SDATA3 INTR AL1 INTR {14}
SDATA#4 U35 AJ1 FERR G Q2 TRST# 510 R16
D SDATA#5 SDATA4 IGNNE NMI_SB IGNNE# {14} FDV301N PLLTEST# 510 R34 D
U33 SDATA5 NMI AN3 NMI_SB {14}
SDATA#6 S37 AG3
SDATA#7 SDATA6 RESET CPURST# {25}
S
S33 SDATA7 SMI AN5 SMI# {14}
SDATA#8 STPCLK# RN11
AA33 SDATA8 STPCLK AC1 STPCLK# {14}
SDATA#9 AE37 DBREQ# 1 2
SDATA#10 SDATA9 TCK
AC33 SDATA10 PWROK AE3 PWRGD_CPU {25} 3 4
SDATA#11 AC37 TMS 5 6
SDATA#12 SDATA11 VCORE TDI
Y37 SDATA12 7 8
SDATA#13 AA37 N1
SDATA#14 SDATA13 PICCLK APICCPU {3}
AC35 N3 8P4R-510
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD0 {14}
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1 {14}
SDATA#16 Q37
SDATA#17 SDATA16 COREFB# C48 RN8
SDATA#18
Q35 SDATA17 COREFB- AG13
COREFB COREFB# {24} Near socket-A SSHIFTEN
N37 AG11 R60 R63 103P 1 2
SDATA#19 SDATA18 COREFB+ COREFB {24} SINTVAL
J33 60.4RST 60.4RST 3 4
SDATA#20 SDATA19 CPUCLK_R SCANCLK2
G33 SDATA20 CLKIN AN17 5 6
SDATA#21 G37 AL17 CPUCLK#_R R64 SCANCLK1 7 8
SDATA#22 SDATA21 CLKIN 301RST
E37 SDATA22
SDATA#23 G35 AN19 CPUCLK_R C44 8P4R-270
SDATA#24 SDATA23 RSTCLK CPUCLK {3}
Q33 AL19 680P
SDATA#25 SDATA24 RSTCLK
N33 SDATA25
SDATA#26 L33 AL21 CLKOUT CPUCLK#_R C45
SDATA#27 SDATA26 K7CLKOUT CPUCLK# {3}
N35 AN21 CLKOUT# 680P
SDATA#28 SDATA27 K7CLKOUT
L37 SDATA28
SDATA#29 J37 VCORE
SDATA#30 SDATA29 VCC2_5 0.5 *
A37 SDATA30 ANALOG AJ13
SDATA#31 E35 VCORE
SDATA#32 SDATA31 VREFMODE VCORE RN6 R20
E31 SDATA32 SYSVREFMODE AA5
SDATA#33 E29 W5 VREF_SYS FID3 1 2 100RST
SDATA#34 SDATA33 VREF_SYS FID2 VREF_SYS
A27 SDATA34 3 4
C SDATA#35 A25 AC5 ZN 100RST 100RST FID1 5 6 C
SDATA#36 SDATA35 ZN ZP FID0 CB4 CB2 R22
E21 SDATA36 ZP AE5 7 8
SDATA#37 C23 100RST
SDATA#38 SDATA37 PLLBP# R59 R54 8P4R-330 39P 104P
C27 SDATA38 PLLBYPASS AJ25
SDATA#39 A23 AN15
SDATA#40 SDATA39 PLLBYPASSCLK
A35 SDATA40 PLLBYPASSCLK AL15
SDATA#41 C35 VCORE
SDATA#42 SDATA41 PLLMON1 100RST 100RST RN10 8P4R-680
C33 SDATA42 PLLMON1 AN13
SDATA#43 C31 AL13 PLLMON2 CPUINIT# 1 2
SDATA#44 SDATA43 PLLMON2 PLLTEST# IGNNE# VCORE
A29 SDATA44 PLLTEST AC3 3 4
SDATA#45 C29 R56 R57 CPURST# 5 6
SDATA#46 SDATA45 C11 39P A20M#
E23 SDATA46 7 8
SDATA#47 C25 S1 SCANCLK1 R30 for internal
SDATA#48 SDATA47 SCANCLK1 SCANCLK2 X_1K VREFSYS
E17 SDATA48 SCANCLK2 S5
SDATA#49 E13 S3 SINTVAL RN9 8P4R-680 VREFMODE
SDATA#50 SDATA49 SCANINTEVAL SSHIFTEN SMI#
E11 SDATA50 SCANSHIFTEN Q5 1 2
SDATA#51 C15 NMI_SB 3 4 R33
SDATA#52 SDATA51 INTR
E9 SDATA52 DBRDY AA1 5 6
SDATA#53 A13 AA3 DBREQ# STPCLK# 7 8 270
SDATA#54 SDATA53 DBREQ FLUSH#
C9 SDATA54 FLUSH AL3
SDATA#55 A9
SDATA#56 SDATA55 TCK FLUSH# R28 680
SDATA#57
C21 SDATA56 TCK Q1
TDI PLLMON1 R50 56
VREFMODE=Low=No voltage scaling
A21 SDATA57 TDI U1
SDATA#58 E19 U5 PLLMON2 R45 56
SDATA#59 SDATA58 TDO TMS
C19 SDATA59 TMS Q3
SDATA#60 C17 U3 TRST# RN36 8P4R-680
SDATA#61 SDATA60 TRST VCORE
A11 SDATA61 1 2
SDATA#62 A17 AIN#0 3 4 ZN R31 40.2RST
SDATA#63 SDATA62 VID0 AIN#1
A15 SDATA63 VID0 L1 VID0 {2