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1 2 3 4 5 6 7 8
01
ZGB Block Diagram
A A
CK505
P2
DDR SYSTEM MEMORY
Pineview
Graphics Interfaces
667 MT/s INT_LVDS
DDRIII-SODIMM 11.6"Panel
CPU CH7036 Up to 1280*800 or 1366*768
P3
P22 P14
P4,5,6,7
DMI
N570 1.66G
HDMI
P22
DMI(x2) Charger
P24
B B
+3VPCU
SATA 0 DMI +5VPCU
SATA - SSD SATA PCIE-4
P18 SIM Card +3V_S5
USB-5 3G/WiMAX
P19 USB-1
P19 +5V_S5
+3V
+5V
PCI-Express(Port1~4) P25
Tigerpoint
VCC_CORE
USB-2 USB 2.0 (Port0~7) P26
CCD PCIE-2
USB PCI-E
P14
SB USB-7 WLAN/WiMAX +1.5VSUS
P19 +SMDDR_VREF
4 in 1 Card Reader USB-4 P8,9,10,11,12,13
Realtek RTS5138 P19 +0.75V_DDR_VTT
RTC +1.5V P27
USB-0,3 SMBUS
C
USB port*2 C
P17 PN : AJ0QMJN0T07
BATTERY +1.05V
P28
USB-6
Bluetooth module P11
P15
+1.5V
Intel High Definition Audio SPI Flash
IHDA P11
Discharge
LPC VCCGFX
P29
LPC
TPM P23
SLB9635TT1.2
Audio Codec Realtek ALC271 EC NPCE781L
P16 P21
D D
Touch Pad /B
K/B Con. Charger SPI Flash Light Sensor
Int. SPK Int. DMIC MIC HP Con.
CONN CONN Jack Jack P15 P24 P21 P15 TSL2561FN P23
Quanta Computer Inc.
PROJECT : ZGB
Size Document Number Rev
Block Diagram 2A
Date: Friday, April 08, 2011 Sheet 1 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
CLK GEN (CLK) 02
VDD_CLK_3.3V VDD_CLK_1.5V +1.5V
+3V R606 2.2/J_6
1 2 L38 +3V
PBY160808T-301Y-N/2A/300ohm_6
L39
PBY160808T-301Y-N/2A/300ohm_6 C766 C767 C768 PM_STPPCI#_R R607 10K/J_4
D <20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress D
Place close to L8 .1U/10V_4 .1U/10V_4 10u/6.3V_6
C769 C770 C771 PM_STPCPU#_R R608 10K/J_4
Place close to L13
C772 .1U/10V_4 .1U/10V_4 .1U/10V_4
0.1uF near every power pin CLKREQ_WLAN#_R R609 10K/J_4
10u/6.3V_6
CLKREQ_3G#_R R610 10K/J_4
U25
0.1uF near every power pin
CLKREQ_Dec#_R R611 10K/J_4
5 23 1/19 : 439549_439549_CorbettPark_Schm_Rev0.5: If this pin is
VDD_REF_3.3 VDD_CORE_1.5 used as PCI_STOP#, it is required to provide a 10-k pull-up to
9 45 Vcc3_3. It is not recommended to connect this signal to the USB_48M R612 20K/F_4
VDD_IO can be ranging VDD_PCI_3.3 VDD_CORE_1.5 Tiger Point(NM10) as it may cause unexpected system behavior.
from 1.05V to 3.3V. 14 CFG input hardware strapping to allocate PLL assignment.
VDD_48M_3.3 LOW = Both CPU and SRC clock drive from PLL3
36 PM_STPPCI#_R R613 *0/J_4 HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
+1.05V PCI_STOP# PM_STPPCI# (11) Contains 100k pull-down resistor.
30 42 PM_STPCPU#_R R614 *Short_4 PM_STPCPU# (11) To SB
VDD_SRC_IO_1.05 CPU_STOP#
VDD_CLKIO_1.05V 35 53
VDD_SRC_IO_1.05 CPU_0 CLK_CPU_BCLK (4)
CPU_0# 52 CLK_CPU_BCLK# (4) To CPU (Core CLK) 166 MHz
R615 *Short_6 L40 48
PBY160808T-301Y-N/2A/300ohm_6 VDD_CPU_IO_1.05
CPU_1 50 CLK_MCH_BCLK (4)
CPU_1# 49 CLK_MCH_BCLK# (4) To CPU (Host CLK) 166 MHz
Place close to L18 1 NC
C773 C774 C775 C776 2 44
NC SRC_1/CPU_ITP CLK_PCIE_Dec (23)
C 13 NC SRC_1/CPU_ITP# 43 CLK_PCIE_Dec# (23) To Decoder 100 MHz C
10U/10V_8 10u/6.3V_6 .1U/10V_4 .1U/10V_4 54 NC
41 T43 USB_48M C777 *10P/50V_4
CG_XOUT SRC_2 T40
3 XTAL_OUT SRC_2# 40
CG_XIN 4
C779 XTAL_IN ITP_EN C778 *10P/50V_4
0.1uF near every power pin SRC_3 38 PE1CLK+ (19)
33P/50V_4 CG_XIN 37 To Mini Card 1 (WLAN) 100 MHz
SRC_3# PE1CLK- (19)
SMBDT1 7
SMBCK1 SDA FSB C780 *10P/50V_4
8 SCL SRC_4 34 CLK_PCIE_DMIP (4)
CL=20p Y8 33 CLK_PCIE_DMIN (4) To CPU (DMI CLK) 100 MHz
SRC_4#
14.318MHz
C782 CLK_BSEL1_FSB R616 1K_4 FSB 15 32 FSC C781 *10P/50V_4
USB48_1/FSB SRC_5 PE4CLK+ (19)
33P/50V_4 CG_XOUT R617 22/J_4 31 To Mini Card 2 (3G/Wimax) 100 MHz
(20) CLK_Card48 SRC_5# PE4CLK- (19)
R618 22/J_4 USB_48M 17
(8) CLKUSB_48 USB48_2 33M_SEL C783 *10P/50V_4
SRC_6 28 CLK_PCIE_ICH (8)
R619 33/J_4 27 To SB (DMI CLK) 100 MHz
(11) 14M_ICH SRC_6# CLK_PCIE_ICH# (8)
FSC 6
CLK_BSEL2_FSC R620 10K_4 REF/FSC DREFCLK
Crystal place within 500mil of CK505 DOT96/SRC7 18 DREFCLK (4)
19 DREFCLK# To CPU (PLL CLK) 96 MHz
DOT96#/SRC7# DREFCLK# (4)
R622 22/J_4 ITP_EN 10
(10) PCLK_ICH PCIF/ITP_EN
R623 22/J_4 20
(19) PCLK_DEBUG LCD_CLK DREFSSCLK (4)
Follow Silego schematic R624 22/J_4 33M_SEL 11 21 To CPU (DPLSS CLK) 100 MHz
(21) LCLK_EC 25MHz/PCI_2/SEL_33MHz LCD_CLK# DREFSSCLK# (4)
R621 22/J_4
(23) PCLK_TPM
SATA 26 CLK_PCIE_SATA (9)
12 VSS_PCI SATA# 25 CLK_PCIE_SATA# (9) To SB (SATA CLK) 100 MHz
16 VSS_48M
B
22 VSS_LCD B
24 47 CLKREQ_Dec#_R R625 475/F_4 Control SRC_1 Register B5b6 for CLKREQ_A#
39
51
VSS_SATA
VSS_SRC
CLKREQ_A#
CLKREQ_B# 46
29
CLKREQ_WLAN#_R
CLKREQ_3G#_R
R626
R627
475/F_4
475/F_4
CLKREQ_Dec# (23)
CLKREQ_WLAN# (19)
Control SRC_3
0 = SRC1, 1=SRC2
Register B5b4 for CLKREQ_B#
Clock Gen I2C
VSS_CPU CLKREQ_C# CLKREQ_3G# (19)
56 0 = SRC3, 1=SRC4
VSS_REF VR_PWRGD_CK410 Control SRC_5 Register B5b3 for CLKREQ_C# +3V
CKPWRGD/PD# 55
57 0 = SRC5, 1=SRC6
Thermal Pad
SLG8LV631V <20100819> Add 475 ohm for current leakage
R628
2.2K_4
2
3 1 SMBCK1
(11,19) PCLK_SMB SMBCK1 (3,19,22,23)
FSC FSB Frequency 2N7002K
0 0 133MHz
VR PWRGD Q30 +3V
0 1 166MHz
1 1 200MHz R629
(26) VR_PWRGD_CK410#
1 0 100MHz 2.2K_4
2
R630 *10K_4
no connect FSA to CPU, due to there is no FSA PIN for CPU. 3 1 SMBDT1
(11,19) PDAT_SMB SMBDT1 (3,19,22,23)
2
R631 *10K/J_4 need to check check how to handle it in CPU CLK_BESEL0
+3V
1 = Pin 43/44as CPU_ITP
A R632 10K/J_4 ITP_EN 0 = Pin 43/44 as SRC_1 R633 *1K_4 1 3 R634 10K_4 2N7002K A
+1.05V +3V
Q31
pin 10 has internal pull down resistor. R635 0_4 CLK_BSEL1_FSB
(4) CPU_BSEL1
2N7002K VR_PWRGD_CK410
VR_PWRGD_CK410 (11)
+3V R636 10K/J_4 R637 *0_4 Q32
R638 *10K/J_4 33M_SEL 1 = Pin 11 as 33MHz Quanta Computer Inc.
0= Pin 11 as 25MHz +1.05V R639 *1K_4
R640 0_4 CLK_BSEL2_FSC <20090721(B2A)> PROJECT : ZGB
(4) CPU_BSEL2 Change Q3,Q5,Q6 from BAM700200F6 to BAM70020002 (with ESD protection function) Size Document Number Rev
R641 *0_4 2A
CLOCK GENERATOR
Date: Friday, April 08, 2011 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
DDR_STD(DDR) +1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] (5)
(5) M_A_A[14:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ5 76 48
M_A_A1 97
A0 DQ0
7 M_A_DQ1
2.48A 81
VDD2 VSS17
49
M_A_A2 A1 DQ1 M_A_DQ7 VDD3 VSS18
96 A2 DQ2 15 82 VDD4 VSS19 54
M_A_A3 95 17 M_A_DQ6 87 55
M_A_A4 A3 DQ3 M_A_DQ4 VDD5 VSS20
92 A4 DQ4 4 88 VDD6 VSS21 60
M_A_A5 91 6 M_A_DQ0 93 61
M_A_A6 A5 DQ5 M_A_DQ2 VDD7 VSS22
90 A6 DQ6 16 94 VDD8 VSS23 65
M_A_A7 86 18 M_A_DQ3 99 66
M_A_A8 A7 DQ7 M_A_DQ8 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 105 72
M_A_A10 A9 DQ9 M_A_DQ10