Text preview for : MS-6714.pdf part of Microstar MS-6714 Microstar MS-6714.pdf
Back to : MS-6714.pdf | Home
8 7 6 5 4 3 2 1
MS-6714 Version 300 Cover Sheet 1
INTEL (R) Brookdale-G/GL/GE/GV Chipset Block Diagram 2
D
Willamette/Northwood 478pin mPGA-B Processor Schematics Clock CY28349 & ATA100 IDE Connector 3 D
CPU: Willamette/Northwood mPGA-478B Processor mPGA478-B INTEL CPU Sockets 4-5
INTEL Brookdale-G GMCH -- North Bridge 6-8
System Brookdale-G / GE / PE Chipset:
INTEL ICH4 -- South Bridge 9 - 10
INTEL GMCH + ICH4
LPC I/O W83627HF-AW 11
On Board Chipset:
FWH 12
BIOS -- FWH
DDR DIMMM1,2 13
LPC Super I/O -- W83627HF-AW
C DDR Damping & DDR Termination 14 C
Clock Generator -- CY28349
AGP 4X SLOT (1.5V) 15
AC'97 Codec -- RealTek AC650
PCI SLOT 1 & 2 & 3 16
Onboard Lan Chipset-- RealTek RTL8101L
IO Connector 17
Expansion Slots: AC'97 Codec and Audio Connector 18
AGP2.0 SLOT * 1 USB Connecto r 19
PCI2.2 SLOT * 3 ACPI Controller (MS-5) 20
B
Platform: Micro ATX L6719B CPU Power ( PWM )-VRM9.0 21 B
Realtek RTL8101L LAN 22
VGA Connector 23
MODEL Config. ORCAD Config. Function Option ERP Number
MS6714GE STD cfg6714GE-STD GE STD STD 601-6714-010 Front Panel & Connectors & FAN 24
MS6714GE Option:L cfg6714GE-LAN GE STD+LAN L 601-6714-020 Jumper Setting & Manual Parts 25
MS6714GV STD cfg6714GV-STD GV STD GV 601-6714-030
GPIO Definition 27-28
MS6714GV Option:L cfg6714GV-LAN GV STD+LAN GVL 601-6714-040
MS6714G STD cfg6714G-STD G STD GB 601-6714-07S Power Delivery Map 29
MS6714G Option:L cfg6714G-LAN G STD+LAN GBL 601-6714-08S
A A
MS6714GL STD cfg6714GL-STD GL STD GL 601-6714-05S
MICRO-STAR
MS6714GL Option:L cfg6714GL-LAN GL STD+LAN GLL 601-6714-06S MSI
Title
COVER SHEET
Size Document Number Rev
300
MS-6714
Date: Monday, January 06, 2003 Sheet 1 of 27
8 7 6 5 4 3 2 1
1
Block Diagram
AGPCLK 66M Z
H
X'TEL
VRM 14.318MHZ ICH_66 66MHZ
P4 478-Pin Processor
Clock 408
INT & PWR-MNG CPUCLK, CPUCLK# 100/13 M Z
3H ICH_PCLK 33MHZ
FWH_PCLK 33M Z
H
SIO_PCLK 33M Z
H
ADDR
CTRL
DATA
MCHCLK, MCHCLK# 100/133 H
MZ
Generator
PCICLK0,1,2,3 33M Z
H
AGTL+ BUS
MCH_66 66MHZ LAN_PCLK 33MHZ
ADDR
CTRL
DATA
SIO_48 48MHZ
DOT_CLK 48MHZ
AGPCLK 66M Z
H ICH_48 48MHZ
ICH_14 14.318MHZ
AGP / ADD AGP BUS
Slot
845G / GL
BGA 760 Pin
DDR1
DDR2
DDR B S
U
VGA BUS
VGA
Connector VCC_AGP 1.5V
VCCP
MEM_STR 2. 5V
HUB LI K
N
BUS
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCICLK0,1,2,3 33M Z
H
ICH_66 66MHZ
A A
IDE Primary UltraDMA 66/100 ICH_PCLK 33MHZ
ICH_48 48MHZ
IDE Secondary
ICH4 ICH_14 14.318MHZ
FW82801DB PCI BUS
RealT ek
AC'97 Link / LAN / EEPROM 8101L
VCC5_SB 5V VCCP
INT & PWR-MNG
CNR Slot VCC3_SB 3.3V VCC3 3.3V LAN_PCLK 33MHZ
VCC1_5SB 1.5V VCC_AGP 1.5V
LAN Chip
LPC BUS
FirmWare
Onboard Hub
FWH_PCLK 33M Z
H
AC'97 Codec SIO_PCLK 33M Z
H BIOS
USB 6 PO T
R
LPC SIO SIO_48 48MHZ
Audio port USB Port 5 USB Port 3 USB Port 1 Mouse Floopy Parallel Game Port MSI MICRO-STAR INT'L CO.,LTD.
Title
USB Port 6 USB Port 4 USB Port 2 Keyboard Serial1,2 Block Diagram
Size Document Number Rev
300
MS-6714
Date: Monday, January 06, 2003 Sheet 2 of 27
1
8 7 6 5 4 3 2 1
CLOCK GENERATOR BLOCK *Trace < 0.5"
CP7 X_COPPER Shut Source Termination Resistors Pull-Down Capacitors
U16 CPUCLK R220 49.9RST
FB18 X_80_0805 VCC3V 39 41 CPU0 R236 27.4RST CPUCLK CPUCLK# R223 49.9RST CPUCLK C153 X_10p
VCC3 CPU_VDD CPUCLK0 40 CPUCLK 4
CPU0# R237 27.4RST CPUCLK# MCHCLK R221 49.9RST
CPUCLK0# CPUCLK# 4
CB137 CB197 CB145 CB169 MCHCLK# R219 49.9RST CPUCLK# C154 X_10p
104P 104P X_10u/0805 104P 36 38 CPU1 R238 27.4RST MCHCLK
CPU_GND CPUCLK1 37 MCHCLK 6
CPU1# R239 27.4RST MCHCLK# MCHCLK C155 X_10p
CPUCLK1# MCHCLK# 6
filtering from 10K~1M
46 Trace less 0.2" MCHCLK# C156 X_10p
MREF_VDD
D
* Put GND copper under Clock Gen. 45 49.9ohm for 50ohm M/B impedance D
CB170 CPUCLK2 44
connect to every GND pin 104P 43 CPUCLK2#
MREF_GND R242 33 MCH_66
* 40 mils Trace on Layer 4 R243 33 AGPCLK MCH_66 6 CLOCK STRAPPING RESISTORS AGPCLK C159 X_10p
32 31
3V66_VDD 3V66_0 30 AGPCLK 15
with GND copper around R244 33 ICH_66 ICH_66 10 ICH_66 C158 X_10p
CB143 3V66_1 28 MCH_66 C157 X_10p
it 104P 29 3V66_2 27 DOT_48 R245 33 DOT_CLK FS0 R266 10K VCC3V
3V66_GND 3V66_48/SEL66_48# DOT_CLK 6
FS3 R269 10K
* put close to every power pin 6 FS2 FS2 R272 10K
* FS2/PCI0 7 FS3 FS4 R274 10K PCICLK3
Trace Width 7mils. 9 7 8
PCI_VDD FS3/PCI1 8 SEL48_1 FS1 R260 1.5K PCICLK0 5 6 CN13
* CB142 SEL48_24#/PCI2 7 8 R258 10K PCICLK1 3 4 X_8P4C-10P
Same Group spacing 15mils 104P 5 10 FS4 RN59 5 6 PCICLK0 BSEL0 4,6 PCICLK2 1 2
* PCI_GND FS4/PCI3 11 8P4R-33 PCICLK1 PCICLK0 16
Different Group spacing 30mils 3 4
PCI4 12 PCICLK1 16
18 1 2 PCICLK2 BSEL0 0 100 ; 1 133
* PCI_VDD PCI5 14 7 8 SIO_PCLK PCICLK2 16
Differentical mode spacing 7mils on itself CB155 PCI6 15 RN60 5 LAN_PCLK SIO_PCLK 11 SIO_PCLK
6 LAN_PCLK 22 2 1
104P 13 PCI7 16 8P4R-33
3 4 FWH_PCLK LAN_PCLK 4 3 CN14
PCI_GND PCI8 17 FWH_PCLK 12 FS4 FS3 FS2 FS1 FS0 FSB (MHz)
1 2 ICH_PCLK FWH_PCLK 6 5 X_8P4C-10P
PCI9 ICH_PCLK 9
1 1 1 0 1 100 MHz ICH_PCLK 8 7
FB19 X_80_0805 VDDA3V 24
VCC3 48_VDD
C163 22 FS0 R267 33 ICH_48 1 1 1 1 1 133 MHz
FS0/48MHz ICH_48 10
CP8 X_COPPER 103P 23 FS1 R261 33 SIO_24 ICH_14 C152 10P
FS1/24_48MHz SIO_24 11
21
48_GND SEL48_1 R270 X_10K VCC3V SIO_24 C178 X_10P
2
CB154 CB156 C181 REF_VDD MUL0 R234 33 ICH_14 ICH_48 C180 X_10P
48 ICH_14 10
104P X_10u/0805 103P MUL0/REF0 1 MUL1 R268 33 CODEC_14 DOT_48 R241 10K
C CODEC_14 18 C
47 MUL1/REF1 CODEC_14C182 X_10P
REF_GND 0 S e t Pin 27 48MHz
34 3 X1 C177 22P DOT_CLK C160 X_10P
C175 CORE_VDD X1
103P X1 14M-32pf-HC49S-D Ioh=6*Iref
33 4 X2 C174 22P
CORE_GND X2 Voh=0.71V
R233 X_10K VCC3V
SMBCLK_ISO 26 35 R240 475RST Iref = 2.32mA MUL0 R222 10K MUL 1:0
11,12,13,20 SMBCLK_ISO SCLK IREF
SMBDATA_ISO 25 0 0 4X
11,12,13,20 SMBDATA_ISO SDATA used only for EMI issue
20 MUL1 R262 10K VCC3V 0 1 5X
R275 10K 19 RESET# 42 PWR_DN# R235 1K VCC3V 1 0 6X
VCC3 VTT_GD# PWR_DN# 1 1 7X Trace less 0.2"
CY28349
R281 220 Q29
VCCP VCC3 VCC3 VCC3 VCC3
2N3904S
CB171 CB123 CB164 CB138 SMBCLK_ISO R252 2.7K VCC3
104P 104P 104P 104P SMBDATA_ISO R253 2.7K
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
B B
IDE1 IDE2
YJ220-CB-1 YJ220-CW-1 SDD[8..15] 10
HD_RST# R190 33 1 2 HD_RST# R189 33 1 2
20 HD_RST#
PDD7 3 4 PDD8 SDD7 3 4 SDD8
10 PDD[0..7] 10 SDD[0..7]
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
PDD[8..15] 10
10 PD_DREQ 21 22 10 SD_DREQ 21 22
23 24 23 24
10 PD_IOW# 10 SD_IOW#
25 26 25 26
10 PD_IOR# 10 SD_IOR#
27 28 27 28
10 PD_IORDY 10 SD_IORDY
29 30 29 30
10 PD_DACK# 10 SD_DACK#
31 32 31 32
9 IRQ14 9 IRQ15
33 34 33 34
10 PD_A1 PD_DET 12 10 SD_A1 SD_DET 12
10 PD_A0 35 36 PD_A2 10 10 SD_A0 35 36 SD_A2 10
37 38 37 38
10 PD_CS#1 PD_CS#3 10 10 SD_CS#1 SD_CS#3 10
39 40 39 40
24 PD_LED 24 SD_LED
R113 R119
R100 C84 R129 15K R99 C97 R132 15K
4.7K X_220P 10K 4.7K X_220P 10K
A VCC5 VCC3 VCC5 VCC3 A
MICRO-STAR
MSI
ATA100 IDE CONNECTORS *
*
*
Trace Width : 5mils
Trace Spacing : 7mils
Length(longest)-Length(shortest)<0.5"
Title
CLOCK GEN & ATA100 IDE
* Trace Length less than 5" Size Document Number Rev
300
MS-6714
Date: Monday, January 06, 2003 Sheet 3 of 27
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
6 HA#[3..31] CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
VID[0..4] 11,21
HA#31
HA#29
HA#24
HA#21
HA#19
HA#14
HA#11
HA#28
HA#25
HA#22
HA#18
HA#15
HA#12
HA#30
HA#27
HA#26
HA#23
HA#20
HA#17
HA#16
HA#13
HA#10
HA#9
HA#8
HA#5
HA#4
HA#7
HA#6
HA#3
AE3 VID2
AE4 VID1
AE5 VID0
AE1 VID4
AE2 VID3
R73
2/3*Vccp 49.9RST
AD26
AC26
AE25
GTLREF1
AB1
M1
M4
M3
M6
W2
W1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
L2
L3
L6
U5A C55 C54 R74
220P 105P 100RST
DBR#
ITP_CLK1
ITP_CLK0
VID4#
VID3#
VID2#