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1 1
HAWAA
2 2
LA-3142PREV 1.0
Schematic
3
uFCPGA Yonah/ ATi-RC410MD(A12)/ ATi-SB450(A13) 3
2006-03-08 Rev. 1.0
om
l.c
4 4
ai
tm
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2005/11/01 Deciphered Date 2006/11/30 Title
in
SCHEMATIC, M/B LA-3141P
xa
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401416 B
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 03, 2006 Sheet 1 of 44
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A B C D E
HAWAA LA-3141 FUNCTION BLOCK DIAGRAM
4
Mobile Yonah 4
uFCPGA-479 Pin Thermal Sensor Clock Generator
CPU VID
ICS951413CGLFT
ADM1032ARM FANController PAGE 32
PAGE 4,5,6 PAGE 4 PAGE 12 PAGE 5
CRT Conn. RTC Battery
FSB
PAGE 15
533MHz/667MHz
PAGE 14
DC/DC InterfacePAGE 33
LCD Conn
PAGE 13 400/533/667MHz LID/Kill Switch
ATI-RC410MD/E (1.8V)
SO-DIMM x 2(DDRII) Power Buttom PAGE 31
Memory Bus BANK 0,1,2,3 PAGE 10,11
LVDS & TV-OUT Conn. VGA M10P Embeded Single channel
PAGE 13
3
707 pin BGA 3
PCI-E X 1 PAGE 7,8,9
DCIN&DETECTOR PAGE 34
A-Link Express x 4
Bandwidth 500MB
2.5GHz(1.2V)
BATT CONN/OTP PAGE 35
Mini Card
FOR WLAN 480MHz(5V) USB 2.0 Port *4 CHARGER PAGE 36
PAGE 23 0,2,4,6 PAGE 27
3V/5V/12V PAGE 37
SATA
3.3V,5V 1.5GHz(150MB/s)
SATA HDD
DDR_1.8V/0.9VEP
PCI BUS
33MHz (3.3V) ATI-SB450 PAGE 17 PAGE 39
564 pin BGA Secondary 1.8VCORE
ATA-100 (5V) PAGE 38
IDE ODD
PAGE 15,16,17,18,19 PAGE 26
2
CARDBUS 1394 LAN 1.5V/PROCHOT 2
PAGE 40
ENE 1410 TSB43AB21 RTL8100CL LPC BUS 33MHz (3.3V)
PAGE 21 PAGE 26 PAGE 20
CPU_CORE PAGE 40
TPM Embedded AZALIA HD CODEC Audio Amplifier
CARD BUS RJ-45 SLB 9635 Controller 24MHz(3.3V) ALC 861 TPA0232 PAGE 25
PAGE 24
SOCKET PAGE 20 PAGE 31 ENE KB910
PAGE 22 PAGE 28
MDC
Connector
PAGE 33
BIOS(1M)
Scan KB
& I/O PORT MOM
PAGE 29 PAGE 30
PAGE 41,42
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/11/01 Deciphered Date 2006/11/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3141P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401416 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 03, 2006 Sheet 2 of 44
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Voltage Rails
Power Plane Description S1 S3 S5 SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) ON ON ON
Full ON HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S1(Power On Suspend) HIGH HIGH ON ON ON LOW
+CPUVID 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF
+1.2VS 1.2VS for PCI-Express ON OFF OFF
+0.9VS 0.9V switched power rail ON OFF OFF S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+1.5VS Yonah ON OFF OFF
S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON*
+1.8V 1.8V power rail ON ON OFF
+3VALW 3.3V always on power rail ON ON ON* Board ID Table for AD channel
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
Vcc 3.3V +/- 5%
+5VS 5V switched power rail ON OFF OFF
Ra/Rc 100K +/- 5%
Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+RTCVCC RTC power ON ON ON
0 0 0 V 0 V 0 V
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
2 2
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
External PCI Devices 7 NC 2.500 V 3.300 V 3.300 V
Device IDSEL# REQ#/GNT# Interrupts
ENE 1410 AD20 2 PIRQB Board ID PCB Revision SKU ID PCB Revision
LAN AD22 1 PIRQG 0 0.1 0 All
1394 AD16 0 PIRQA 1 0.2 1
2 2
3 3
4 4 JP
5 5
6 6
7 7
3 EC SM Bus1 address EC SM Bus2 address 3
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 110X b BTN ID BTN Status BTO Function BOM structure
0 1 Buttons 1394 1394@
1 Wireless LAN WLAN@
2 TV-OUT TVOUT@
3 TPM TPM@
4 6 Buttons
SB450 SM Bus address 5
6
Device Address 7
Clock Generator
(ICS951413BGLFT) 1101 001Xb
DDRII DIMM0 1010 0100b A4
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DDRII DIMM1 1010 0110b A6
l.c
4 4
ai
tm
ho
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2005/11/01 Deciphered Date 2006/11/30 Title
in
SCHEMATIC, M/B LA-3141P
xa
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401416 B
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 03, 2006 Sheet 3 of 44
A B C D E
5 4 3 2 1
<7> H_A#[3..31] H_D#[0..63] <7>
JCPU1A
+3VS
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +1.05VS +CPU_CORE
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23 1
1
1
1
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 @ R463 R464 C663 R465
D J1 A9# D6# E25 D
H_A#10 N3 E23 H_D#7 47K_0402_5% 0.1U_0402_16V4Z @ 10K_0402_5%
H_A#11 A10# D7# H_D#8 47K_0402_5% 2
P5 A11# D8# K24
H_A#12 P2 G24 H_D#9 1
MAINPWON <16,34,35,37>
2
2
2
H_A#13 A12# D9# H_D#10 C664 U31
L1 A13# D10# J24
1
H_A#14 P4 J23 H_D#11 H_THERMDA 2 1
H_A#15 A14# D11# H_D#12 Q53 2200P_0402_50V7K D+ VDD1
P1 A15# D12# H26 1 2 2
H_A#16 H_D#13 @ 0.1U_0603_25V7K MMBT3904_SOT23 2 H_THERMDC 3
R1 A16# D13# F26 D- ALERT# 6
H_A#17 Y2 K22 H_D#14 C665
3
H_A#18 A17# D14# H_D#15
U5 A18# D15# H25 <28> EC_SMB_CK2 8 SCLK THERM# 4
H_A#19 R3 N22 H_D#16
H_A#20 A19# D16# H_D#17
W6 A20# D17# K25 <28> EC_SMB_DA2 7 SDATA GND 5
H_A#21 U4 P26 H_D#18 +1.05VS 1 2
H_A#22 A21# D18# H_D#19 R466
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20 56_0402_5% ADM1032ARM_RM8
H_A#24 A23# D20# H_D#21 H_THERMTRIP#
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26
H_A#27
H_A#28
T3
W3
A25#
A26#
A27#
D22#
D23#
D24#
M23
P25
H_D#23
H_D#24
H_D#25
A
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26
H_A#30 A29# D26# H_D#27
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28
<7> H_REQ#[0..4] A31# D28#
L26 H_D#29
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32 +3VALW
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 +1.05VS
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
1
V26 H_D#35 +1.05VS
H_ADSTB#0 D35# H_D#36
<7> H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37 R467
<7> H_ADSTB#1 ADSTB1# D37#
2
C H_D#38 330_0402_5% C
D38# U25
1
1
U22 H_D#39
2
D39# H_D#40 R468 R469 R470
D40# AB25
W22 H_D#41 470_0402_5% 75_0402_5% @ 56_0402_5%
D41# H_PROCHOT# <16>
Y23 H_D#42
1
CLK_BCLK D42# H_D#43 H_DPRSTP# 2
<12> CLK_BCLK A22 AA26 1
2
2
BCLK0 D43#
1
CLK_BCLK# A21 HOST CLK Y26 H_D#44 R471 0_0402_5% C
<12> CLK_BCLK# BCLK1 D44#
B
1
Y22 H_D#45 2 Q54
D45# H_D#46 Q55 B @ PMBT3904_SOT23
D46# AC26 2 1 2 DPRSLPVR <15,40>
AA24 H_D#47 MMBT3904_SOT23 R472 470_0402_5% E
3
H_ADS# D47# H_D#48
<7> H_ADS# H1 AC22
3
H_BNR# ADS# D48# H_D#49 PROCHOT#
<7> H_BNR# E2 BNR# D49# AC23
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI#
<7> H_BR0#
<7> H_DEFER#
H_BR0#
H_DEFER#
H _DRDY#
F1
H5
BPRI#
BR0#
DEFER#
D50#
D51#
D52#
AA21
AB21
H_D#51
H_D#52
H_D#53
C
<7> H_DRDY# F21 DRDY# D53# AC25
H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
H_LOCK# IERR# D56# H_D#57