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A B C D E

Compal Confidential
Model Name : P5WE0
File Name : LA-6901P
1 1

BOM P/N:43

Compal Confidential
2 2

P5WE0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV

3 2010-08-11 3

REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WE0 M/B LA-6901P Schematic
Date: Friday, August 27, 2010 Sheet 1 of 59
A B C D E
A B C D E

Fan Control
page 38

1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
N12P GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 12,13
1.5V DDRIII 1066/1333
Processor
page23~31

rPGA989
page 5~11

HDMI(DIS) CRT(DIS) LVDS(DIS) FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera 3G connector
Conn USB port 9,12 on 3G/B
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
USB port 0,1 on USB port 13 USB port 10
USB/B page 39 page 39 page 32 page 32
page 34 page 33 page 32 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS) HD Audio 3.3V 24MHz

TMDS(UMA/OPTIMUS) Cougar Point-M
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
989pin BGA ALC271X/277X
port 5 port 2,3 port 1 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz SPI page 43
page 14~22

MINI Card x2 LAN(GbE) &
USB 3.0 conn x1
WLAN, WWAN Card Reader
USB port 12,13 BCM57785
page 45 page 38 page 36 SPI ROM x1 Int. Speaker Phone Jack x 2
port 0,1 port 2 page 14
page 44 page 44
SATA HDD SATA CDROM
3
Card Reader RJ45 Conn. page Conn. page 35 LPC BUS 3
35
Conn. page 37
page 37
33MHz

Sub-board ENE KB930
page 40
LS-6901P LF-6901P
USB 2.0/B 2Port
RTC CKT. USB Port0,1 page 39
FPC for USB3.0
CPU XDP
page 14
Touch Pad Int.KBD
page 41 page 6
page 41
LS-6902P
Power On/Off CKT. PWR/B
page 42 PCH XDP
page 39
BIOS ROM page 14
page 40
DC/DC Interface CKT. LS-6903P
4 page 46 3G/B 4

page 41

Power Circuit DC/DC
LS-6904P
page 48~56 USB 3.0 /B Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/11 2011/08/11 Title
1 port as USB3.0 Issued Date Deciphered Date
Block Diagrams
1 port as USB2.0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
page 41 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WE0 M/B LA-6901P Schematic
Date: Friday, August 27, 2010 Sheet 2 of 59
A B C D E
A B C D E

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V EVT
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V Pre-MP
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Board ID PCB Revision
UMA Only UMAO@
0 0.1
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
UMA with OPTIMUS UMA@
1 0.2
Dis with OPTIMUS DIS@
EC SM Bus1 address EC SM Bus2 address 2 0.3
DIS Only DISO@
3 1.0
Device Address Device Address
OPTIMUS OPT@
4
Smart Battery 0001 011X b
Non-OPTIMUS NOPT@
5
3G 3G@
6
Blue Tooth BT@
7
USB2.0 USB20@
PCH SM Bus address USB3.0 USB30@
3 VRAM X76@ 3
Device Address
USB Port Table Connector CONN@
Clock Generator (9LVS3199AKLFT, 1101 0010b Unpop @
RTM890N-631-VB-GRT) 3 External
DDR DIMM0 1001 000Xb
USB 2.0 USB 1.1 Port USB Port LAN Chip A0 version A0@
DDR DIMM2 1001 010Xb
LAN Chip B0 version B0@
0 USB/B (Right Side)
UHCI0
1 USB/B (Right Side)
3G & BT & USB30 & USB20 Config
2 USB 2.0 & USB3.0 Conn.
3G SKU: 3G@ USB30 SKU: USB30@ OPTMIUS SKU: OPT@ UHCI1
3
BT SKU: BT@ USB20 SKU: USB20@ Non-OPTMIUS SKU: NOPT@ EHCI1
4
LAN Chip A0 version: A0@ UHCI2
5
LAN chip B0 Version: B0@
6
UHCI3
7
BOM Config 8 Mini Card 1(WLAN)
UHCI4
UMA Only: BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@ 9 3G/B(WWAN)
OPTIMUS: BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@ 10 Camera
EHCI2 UHCI5
DIS Only: BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@ 11 Mini Card 2(Reserved)
4 4
VRAM BOM Config 12 SIM Card (3G/B)
UHCI6
X76***BOL01: Samsung 13 Blue Tooth
X76***BOL02: Hynix

VRAM P/N : Security Classification Compal Secret Data Compal Electronics, Inc.
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) Issued Date 2010/08/11 Deciphered Date 2011/08/11 Title
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WE0 M/B LA-6901P Schematic
Date: Friday, August 27, 2010 Sheet 3 of 59
A B C D E
5 4 3 2 1

+1.05VS_VTT
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,

1
max length = 500 mils,trace width=4mils
R517
24.9_0402_1% PEG_ICOMPO signals should be routed with - max
JCPU1A
length = 500 mils,trace width=12mils

2
D
PEG_ICOMPI J22 PEG_COMP spacing =15mils D

PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] H22
PEG_RCOMPO
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33PEG_GTX_C_HRX_N15 C46 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N15
M35PEG_GTX_C_HRX_N14 PEG_GTX_HRX_N14
PEG_RX#[1] C49 1 2 DIS@ 0.22U_0402_10V6K
15 DMI_CRX_PTX_P0 B28 DMI_RX[0] PEG_RX#[2] L34PEG_GTX_C_HRX_N13 C51 1 2 DIS@ 0.22U_0402_10V6K
PEG_GTX_HRX_N13
15 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35PEG_GTX_C_HRX_N12 C53 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N12

DMI
PEG_GTX_C_HRX_N11 C60 1 PEG_GTX_HRX_N11
15 DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32
PEG_GTX_C_HRX_N10 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N10 PEG_GTX_HRX_N[0..15] 22
15 DMI_CRX_PTX_P3 B23 H34 C71 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N9 PEG_GTX_HRX_P[0..15] 22
DMI_RX[3] PEG_RX#[5] PEG_GTX_C_HRX_N9
PEG_RX#[6] H31 C75 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N8
PEG_GTX_C_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] G33 C82 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N[0..15] 22
PEG_RX#[7] PEG_GTX_C_HRX_N7 PEG_GTX_HRX_N7
15 DMI_CTX_PRX_N1 E22 DMI_TX#[1] G30 C92 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P[0..15] 22
PEG_RX#[8] PEG_GTX_C_HRX_N6 C93 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
15 DMI_CTX_PRX_N2 F21 DMI_TX#[2] F35
PEG_RX#[9] PEG_GTX_C_HRX_N5 PEG_GTX_HRX_N5
15 DMI_CTX_PRX_N3 D21 DMI_TX#[3] E34 C102 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N4
PEG_RX#[10] PEG_GTX_C_HRX_N4
PEG_RX#[11] E32PEG_GTX_C_HRX_N3 C111 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N3
15 DMI_CTX_PRX_P0 G22 DMI_TX[0] D33 C113 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N2
PEG_RX#[12] PEG_GTX_C_HRX_N2
15 DMI_CTX_PRX_P1 D22 DMI_TX[1] D31PEG_GTX_C_HRX_N1
C125 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N1
PEG_RX#[13]

PCI EXPRESS* - GRAPHICS
15 DMI_CTX_PRX_P2 F20 DMI_TX[2] B33PEG_GTX_C_HRX_N0 C129 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N0
PEG_RX#[14]
15 DMI_CTX_PRX_P3 C21 DMI_TX[3] C32 C144 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX#[15]
PEG_GTX_C_HRX_P15 PEG_GTX_HRX_P15
PEG_RX[0] J33 PEG_GTX_C_HRX_P14 C47 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P14
PEG_RX[1] L35PEG_GTX_C_HRX_P13 C50 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P13
PEG_RX[2] K34PEG_GTX_C_HRX_P12 C52 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] H35PEG_GTX_C_HRX_P11 C56 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX[3] PEG_GTX_HRX_P11
15 FDI_CTX_PRX_N1 H19 FDI0_TX#[1] H32PEG_GTX_C_HRX_P10 C66 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P10
PEG_RX[4]
15 FDI_CTX_PRX_N2 E19 FDI0_TX#[2] G34PEG_GTX_C_HRX_P9 C68 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P9
PEG_RX[5]

Intel(R) FDI
C 15 FDI_CTX_PRX_N3 F18 FDI0_TX#[3] G31PEG_GTX_C_HRX_P8 C81 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P8 C
PEG_RX[6]
15 FDI_CTX_PRX_N4 B21 F33PEG_GTX_C_HRX_P7 C86 1
C20
FDI1_TX#[0] PEG_RX[7] 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] F30PEG_GTX_C_HRX_P6 C89 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P6
15 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] E35PEG_GTX_C_HRX_P5 C100 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P5
PEG_RX[9]
15 FDI_CTX_PRX_N7 E17 E33PEG_GTX_C_HRX_P4 C105 1
FDI1_TX#[3] PEG_RX[10] 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P4
F32PEG_GTX_C_HRX_P3 C106 1 PEG_GTX_HRX_P3
PEG_RX[11] 2 DIS@ 0.22U_0402_10V6K
D34PEG_GTX_C_HRX_P2 C117 1 PEG_GTX_HRX_P2
A22
PEG_RX[12] 2 DIS@ 0.22U_0402_10V6K
15 FDI_CTX_PRX_P0 FDI0_TX[0] E31PEG_GTX_C_HRX_P1 C119 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P1
PEG_RX[13]
15 FDI_CTX_PRX_P1 G19 C33 C135 1
FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P0
15 FDI_CTX_PRX_P2 E20 FDI0_TX[2] B32 C138 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3] PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 B20 M29PEG_HTX_GRX_N14 C516 2 DIS@ 0.22U_0402_10V6K
15 FDI_CTX_PRX_P5 C19
FDI1_TX[0] PEG_TX#[0]
M32PEG_HTX_GRX_N13 C520 1 1 2 DIS@ 0.22U_0402_10V6K
PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P6 D19
FDI1_TX[1] PEG_TX#[1]
M31PEG_HTX_GRX_N12
C529 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N13
FDI1_TX[2] PEG_TX#[2] PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 F17 FDI1_TX[3] L32 PEG_HTX_GRX_N11 C534 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N11
PEG_TX#[3]
+1.05VS_VTT PEG_TX#[4] L29 PEG_HTX_GRX_N10 C538 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 K31PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9
FDI0_FSYNC PEG_TX#[5] C540 1 2 DIS@ 0.22U_0402_10V6K
15 FDI_FSYNC1 J17 K28PEG_HTX_GRX_N8 C542 DIS@ 0.22U_0402_10V6K
FDI1_FSYNC PEG_TX#[6] C544 1 1 2 2DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N8
PEG_TX#[7] J30 PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7
eDP_COMPIO and ICOMPO signals should 15 FDI_INT H20 FDI_INT J28 PEG_HTX_GRX_N6 C546 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N6
PEG_TX#[8] C548 1 2 DIS@ 0.22U_0402_10V6K
be shorted near balls, H29PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5
1

15 FDI_LSYNC0 J19 PEG_TX#[9] C550 1 2 DIS@ 0.22U_0402_10V6K
FDI0_LSYNC G27 PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4
Trace Width for EDP_COMPIO=4mils, R145 15 FDI_LSYNC1 H17 PEG_TX#[10]
E29PEG_HTX_GRX_N3
C552 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N3
24.9_0402_1% FDI1_LSYNC PEG_TX#[11]
EDP_ICOMPO=12mils, PEG_TX#[12] F27PEG_HTX_GRX_N2 C554 1 PEG_HTX_C_GRX_N2
D28 2 DIS@ 0.22U_0402_10V6K
and both length less than 500 mils... PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1
PEG_TX#[13]